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WM8775

w

PP Rev 1.8, June 2004

9

BCLK

ADCLRC

t

BCH

t

BCL

t

BCY

DOUT

t

LRSU

t

LRH

t

DD

Figure 5 Digital Audio Data Timing – Slave Mode

Test Conditions

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

50

ns

BCLK pulse width high

20

ns

BCLK pulse width low

20

ns

ADCLRC set-up time to

BCLK rising edge

10

ns

ADCLRC hold time from

BCLK rising edge

10

ns

DOUT propagation delay

from BCLK falling edge

0

10

ns

Table 3 Digital Audio Data Timing – Slave Mode

Note:

ADCLRC should be synchronous with MCLK, although the WM8775 interface is tolerant of phase variations or jitter on

these signals.