WM9709

Production Data

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PD Rev 1.3 February 2003

12

SYNC

BITCLK

SDATAIN

WM9709 SAMPLES SYNC ASSERTION

AC-LINK CONTROLLER SAMPLES

FIRST SDATAIN BIT OF FRAME

END OF PREVIOUS AUDIO FRAME

DAC

READY

SLOT(1)

SLOT(2)

Figure 10 Start of an Audio Input Frame

SDATAIN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0’s by the WM9709. SDATAIN is sampled on

the falling edges of BITCLK.

SLOT 1: STATUS ADDRESS PORT

Audio input frame slot 1 echoes the control register index from the read request, for historical

reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid”

by WM9709 during slot 0).

STATUS ADDRESS PORT BIT ASSIGNMENTS:

Bit(19)

RESERVED (stuffed with 0s)

Bit(18:12)

Control register index (echo of register index for which data is

being returned)

Bit(11:0)

RESERVED (stuffed with 0s)

The first bit (MSB) generated by WM9709 is always stuffed with a 0. The following 7 bit positions

communicate the associated control register address, and the trailing 12-bit positions are stuffed

with 0s by WM9709

SLOT 2: STATUS DATA PORT

The status data port delivers 16-bit control register read data.

Bit(19:4)

Control register read data (stuffed with 0s if tagged “invalid” by

WM9709)

Bit(3:0)

RESERVED (stuffed with 0s)

If slot 2 is tagged “invalid” by WM9709, then the entire slot will be stuffed with 0s.

The WM9709 will use this port only to return the data value of the vendor ID.

SLOTS 3-12: UNUSED

The remaining slots in the audio input frame are not used by the WM9709. All bits in these slots will

be stuffed with 0s.

AC-LINK LOW POWER MODE

Not supported by WM9709