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ICS9DB104 数据表(PDF) 4 Page - Integrated Circuit Systems |
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ICS9DB104 数据表(HTML) 4 Page - Integrated Circuit Systems |
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4 / 13 page ![]() 4 Integrated Circuit Systems, Inc. ICS9DB104 0767C—07/19/04 Absolute Max Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage 4.6 V VDD_In 3.3V Logic Supply Voltage 4.6 V VIL Input Low Voltage GND-0.5 V VIH Input High Voltage VDD+0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase Case Temperature 115 °C ESD prot Input ESD protection human body model 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V Input Low Voltage VIL 3.3 V +/-5% GND - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 uA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA Operating Supply Current IDD3.3OP Full Active, CL = Full load; 200 mA all diff pairs driven 40 mA all differential pairs tri-stated 12 mA Input Frequency 3 Fi VDD = 3.3 V 80 100/133 166/200 220 MHz 3 Pin Inductance 1 Lpin 7nH 1 CIN Logic Inputs 1.5 5 pF 1 COUT Output pin capacitance 6 pF 1 PLL Bandwidth when PLL_BW=0 4MHz 1 PLL Bandwidth when PLL_BW=1 2MHz 1 Clk Stabilization 1,2 TSTAB From VDD Power-Up and after input clock stabilization or de- assertion of PD# to 1st clock 1ms 1,2 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_SRC_STOP# DIF output enable after SRC_Stop# de-assertion 10 ns 1,3 Tdrive_PD# DIF output enable after PD# de-assertion 300 us 1,3 Tfall Fall time of PD# and SRC_STOP# 5ns 1 Trise Rise time of PD# and SRC_STOP# 5ns 2 1Guaranteed by design and characterization, not 100% tested in production. 2See timing diagrams for timing requirements. IDD3.3PD 3Time from deassertion until outputs are >200 mV Input Capacitance 1 Input Low Current Powerdown Current PLL Bandwidth BW |
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