MDS 1526 I

6

Revision 020304

Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201

www.icst.com

Section 3 Register map summary

ICS1526 Preliminary Data Sheet

07h

Osc_Div

R / W

Osc_Div 0-6

0-6

0

Osc Divider modulus

Minimum 3 =0000001 binary, Maximum 129 = 1111111 binary

Divider setting = 7-bit word + 2

In-Sel

7

0

Input Select

0=HSYNC Input, 1=OSC Input

OSC input clock must be present to select OSC input

08h

Reset

Write

PLL

0-7

x

Writing 5Ah resets PLL and commits values written to word

addresses 01h-03h and 05h

09-0Fh

Reserved

Read

Reserved

0-7

Reserved

10h

Chip Ver

Read

Reserved

0-7

Reserved

11h

Chip Rev

Read

Chip Rev

0-7

01

Reserved

12h

Rd_Reg

Read

Reserved

0

N/A

Reserved

PLL_Lock

1

N/A

PLL Lock Status

0=Unlocked, 1=Locked

Reserved

2-7

0

Reserved

*. Written values to these registers do not take effect immediately, but require a commit via register 08h

Word

Address

Name

Access

Bit Name

Bit#

Reset

Value

Description