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IRU3138CS 数据表(PDF) 9 Page - International Rectifier |
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IRU3138CS 数据表(HTML) 9 Page - International Rectifier |
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9 / 18 page ![]() IRU3138 9 Rev. 1.0 01/29/04 www.irf.com Choose IRLR3715Z for control MOSFET and IRFR3711Z for synchronous MOSFET. These devices provide low on-resistance in a D-Pak. The MOSFETs have the following data: The total conduction losses will be: The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switch- ing losses in synchronous Buck converter. The synchro- nous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: The switching time waveform is shown in Figure 7. Figure 7 - Switching time waveforms. From IRFR3711Z data sheet we obtain: These values are taken under a certain condition test. For more details please refer to the IRFR3711Z datasheet. By using equation (12), we can calculate the total switch- ing losses. Feedback Compensation The IRU3138 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensa- tion circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45 8). The output LC filter introduces a double pole, –40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 8 (see Figure 8). The Reso- nant frequency of the LC filter is expressed as follows: Figure 9 shows gain and phase of the LC filter. Since we already have 180 8 phase shift just from the output filter, the system risks being unstable. Figure 8 - Gain and phase of LC filter. PCON(TOTAL) = PCON(UPPER) + PCON(LOWER) PCON(TOTAL) = 1.77W PSW(TOTAL) = 336mW Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW = ILOAD ---(12) 3 VDS(OFF) 2 tr + tf T 3 IRFR3711Z tr = 13ns tf = 15ns FLC = ---(13) 1 2 p3 LO 3CO VDS VGS 10% 90% td(ON) td(OFF) tr tf Gain FLC 0dB Phase 0 8 FLC -180 8 Frequency Frequency -40dB/decade IRFL3715Z VDSS = 20V RDS(ON) = 11mV IRFR3711Z VDSS = 20V RDS(ON) = 5.7mV |
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