PD035VX2

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Note 5-3: Select left or right shift

R/L

DIO1

DIO2

Shift

1

Input

Hi-Z

Left to right

0

Hi-Z

Input

Right to left

Note 5-4: Gate driver shift clock

Under this condition, the operation of registers will not be affected.

Note 5-6: Select up or down shift

U/D

STVU

STVD

Shift

1

Hi-Z

Input

Down to Up

0

Input

Hi-Z

Up to Down

Note 5-7 Latch the polarity of outputs and switch the new data to outputs

At the rising edge (LD), latch the “POL” signal to control the polarity of the outputs.

Note 5-8 Control whether the Data R0~G5 are inverted or not. (PVI suggests connecting to GND)

When “REV=1”, these data will be inverted.

EX: “00”→”3F”, “07”→”38”, “15”→”2A”

Note 5-9: Polarity selector for dot-inversion control. Available at the rising edge of LD.

When POL=1: Even outputs range from V1~V7, and Odd outputs range from V8~V14;

When POL=0: Even outputs range from V8~V14, and Odd outputs range from V1~V7.