IC-MB4 datasheet(21/40 Pages) ICHAUS

21 / 40 page

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iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 21/40

Figure 14: BiSS B register access (EN_MO = 1)

Extended SSI BiSS C Register Communication

With extended SSI the BiSS C register write access is

possible to the SSI slave. The master is able to transmit

a BiSS C register write access to the slave without the

slaves CDS feedback. The master cannot verify if the

BiSS C register write access to the slave did succeed

or not. At the end of the cycle the master sends the

CDM bit inverted on the MA clock line.

BiSS C Init Sequence

In the init sequence two 0 pulses are generated at MA.

The slave should answer with a falling edge and after

the BiSS timeout with a rising edge at SL. The gap

between the second rising edge at MA and the falling

edge at SL is measured as line delay and stored in the

single cycle data RAM. The BiSS C init is selected with

REGVERS=1 and executed with INIT = 1.

Figure 15: BiSS init sequence

With an INIT sequence the iC-MB4 does store the mea-

sured channel 1 line delay in the SCDATA1(7:0) and

the channel 2 line delay in the SCDATA5(7:0).

The unit of this value is the 1/4 of the configured MA

clock frequency.

tLine Delay Channel 1 =

SCDATA1(7:0)

4∗f MA

tLine Delay Channel 2 =

SCDATA5(7:0)

4∗f MA

For the INIT sequence the maximum line delay is 255.

On exceeding this limit while INIT the INIT sequence is

aborted and an AGSERR is set.

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