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STA304A 数据表(PDF) 21 Page - STMicroelectronics |
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STA304A 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 30 page ![]() 21/30 STA304A 12.3 Tone Control Register (add. 08h) This register support tone controls (bass and treble). The step size is 2dB. Writing a 0000h corresponds to +12dB of gain. Center frequencies (from which gains are measured) are 160Hz for Bass and 5,000Hz for Treble. The default value is 0F0Fh, which corresponds to bypass of bass or treble gain. The tone feature is implemented only on the L and R front channel. 12.4 Powerdown Ctrl/Staus Register (PCSR) : add. 26h NOTE: Bits D0..D3 will be masked to the showed value before writing into the RAM registers, other bits will simply pass through. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXX BA3 BA2 BA1 BA0 XXXX TR3 TR2 TR1 TR0 TR3... TR0 or BA3... BA0 Function 0000 +12 dB of gain 0001 +10 dB of gain 0010 +8 dB of gain 0011 +6 dB of gain 0100 +4 dB of gain 0101 +2 dB of gain 0110 +1 dB of gain 0111 0 dB of gain 1000 -1 dB of gain 1001 -2 dB of gain 1010 -4 dB of gain 1011 -6 dB of gain 1100 -8 dB of gain 1101 -10 dB of gain 1110 -12 dB of gain 1111 Bypass D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EAPD PR5 PR4 1110 BIT R/W RST NAME DESCRIPTION 12 R/W 0 PR4 Setting this bit to 1 the BIT_CLK and the SDATA_IN signal will be fixed to the digital low level. To resume the normal operation either an hardware reset or a softReset must be performed. 13 R/W 0 PR5 In order to set the device in a powerdown-like condition this bit must be set to 1. This will stop the device internal clock: only the PLL and AC`97, I2C clocks will still be running. DSP should start power-down sequence in order to accomplish this request. 15 R/W 1 EAPD The value of this bit should be checked by the DSP in order to recognize an external power amplifier power-down request. As a consequence the DSP should start the power-down sequence (volume fade-out) |
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