LAN91C100FD datasheet(39/79 Pages) SMSC

39 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 39

Rev. 10/14/2002

PRELIMINARY

FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure.

When 0, RD0-RD7 is always driven. When 1, RD0-RD7 is floated during RECEIVE FRAME STATUS

WORD writes (RA2-RA16=0, RCVDMA=1, nRWE0-nRWE3=0).

MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).

MDO - MII Management output. The value of this bit drives the MDO pin.

MDI - MII Management input. The value of the MDI pin is readable using this bit.

MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.

MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.

The purpose of this interface, along with the corresponding pins is to implement MII PHY management in

software.

BANK 3

OFFSET

NAME

TYPE

SYMBOL

REVISION REGISTER

READ ONLY

REV

HIGH

BYTE

LOW

BYTE

CHIP

REV

CHIP - Chip ID. Can be used by software drivers to identify the device used.

REV - Revision ID. Incremented for each revision of a given device.

OFFSET

NAME

TYPE

SYMBOL

EARLY RCV REGISTER

READ/WRITE

ERCV

HIGH

BYTE

nRXDISC PIN COUNTER

LOW

BYTE

RCV

DISCR

ERCV THRESHOLD

nRXDISC PIN COUNTER - 8-bit counter increments when a packet is discarded due to the nRXDISC pin

being active. This counter will be reset to 00 when read. A count of FF will set the RX_DISC INT. The

count will wrap around to 00 after FF.

RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being

received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will

be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0

set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.

ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the number

of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT

bit of the INTERRUPT STATUS REGISTER is set.

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