HCS412TP datasheet(11/44 Pages) MICROCHIP

11 / 44 page

Preliminary

DS41099C-page 11

HCS412

3.2.2

CYCLE REDUNDANCY CHECK (CRC)

The CRC bits may be used to check the received data

integrity, but it is not recommended when operating

near the low voltage trip point, see Note below.

The CRC is calculated on the 65 previously transmitted

bits (Figure 3-2), detecting all single bit and 66% of all

double bit errors.

EQUATION 3-1:

CRC CALCULATION

3.2.3

LOW VOLTAGE DETECTOR STATUS

(VLOW)

The low voltage detector result is included in every

transmitted code word.

The HCS412 samples the voltage detector output at

the onset of a transmission and just before the VLOW

bit is transmitted in each code word. The first sample is

used in the CRC calculation and the subsequent sam-

ples determine what VLOW value will be transmitted.

The transmitted VLOW status will be a ‘0’ as long as

VDD remains above the selected low voltage trip point.

VLOW will change to a ‘1’ if VDD drops below the

selected low voltage trip point.

TABLE 3-2:

LOW VOLTAGE STATUS BIT

TABLE 3-3:

LOW VOLTAGE TRIP POINT

SELECTION OPTIONS

3.2.4

COUNTER OVERFLOW BITS (OVR1,

OVR0)

The Counter Overflow Bits may be utilized to increase

the synchronization counter range from the nominal

65,535 to 131,070 or 196,605.

The bits must be programmed during production as ‘1’s

to be utilized. OVR0 is cleared the first time the syn-

chronization counter wraps from FFFFh to 0000h.

OVR1 is cleared the second time the synchronization

counter wraps to zero. The two bits remain at ‘0’ after

all subsequent counter wraps.

3.2.5

EXTENDED SERIAL NUMBER (XSER)

The Extended Serial Number option determines

whether the serial number is 28 or 32 bits.

When configured for a 28-bit serial number, the most

significant nibble of the 32 bits reserved for the serial

number is replaced with a copy of the 4-bit button sta-

tus, Figure 3-2.

3.2.6

DISCRIMINATION VALUE (DISC)

The Discrimination Value is a 10-bit fixed value typi-

cally used by the decoder in a post-decryption check.

It may be any value, but in a typical system it will be

programmed as the 10 Least Significant bits of the

serial number.

The discrimination bits are part of the information that

form the encrypted portion of the transmission

(Figure 3-2). After the receiver has decrypted a trans-

mission, the discrimination bits are checked against

the receiver’s stored value to verify that the decryption

process was valid. If the discrimination value was pro-

grammed equal to the 10 LSb’s of the serial number

then it may merely be compared to the respective bits

of the received serial number.

3.2.7

SEED CODE WORD DATA FORMAT

The Seed Code Word transmission allows for what is

known as a secure learning function, increasing a sys-

tem’s security.

The seed code word also consists of 69 bits, but the 32

bits of code hopping data and the 28 bits of fixed data

are replaced by a 60-bit seed value that was stored

during production (Figure 3-4). Instead of using the

normal key generation inputs to create the crypt key,

this seed value is used.

Seed transmissions are either:

• permanently enabled

• permanently disabled

• temporarily enabled (limited) until the 7 Least Sig-

nificant bits of the synchronization counter wrap

from 7Fh to 00h.

The Seed Enable (SEED) and Temporary Seed Enable

(TMPSD) configuration options control the function

(Table 3-4).

Note: The CRC may be wrong when the operat-

ing voltage is near VLOW trip point. VLOW is

sampled twice each transmission, once for

the CRC calculation (DATA output is LOW)

and once when the VLOW bit is transmitted

(DATA output is HIGH). VDD varying slightly

during a transmission could lead to a differ-

ent VLOW status transmitted than that used

in the CRC calculation.

Work around:

If the CRC is incorrect,

recalculate for the opposite value of VLOW.

VLOW

Description

0VDD is above trip voltage (VLOWSEL)

1VDD is below trip voltage (VLOWSEL)

VLOWSEL

Nominal

Trip

Point

Description

2.2V

for 3V battery applications

4.4V

for 6V battery applications

CRC 1

[]

CRC 0

[]

⊕

CRC 0

[]

CRC 0

[]

⊕

() CRC 1

[]

⊕

CRC 1 0

[]

and

with

and Din the nth transmission bit 0 ≤ n ≤ 64

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