LPC2124FBD64 datasheet(7/34 Pages) PHILIPS

7 / 34 page

Philips Semiconductors

LPC2114/LPC2124

Single-chip 16/32-bit microcontrollers

Product data

Rev. 03 — 22 December 2004

7 of 34

9397 750 13145

P0.28

AIN1 — A/D converter, input 1. This analog input is always connected to its

pin.

CAP0.2 — Capture input for Timer 0, channel 2.

MAT0.2 — Match output for Timer 0, channel 2.

P0.29

AIN2 — A/D converter, input 2. This analog input is always connected to its

pin.

CAP0.3 — Capture input for Timer 0, Channel 3.

MAT0.3 — Match output for Timer 0, channel 3.

P0.30

AIN3 — A/D converter, input 3. This analog input is always connected to its

pin.

EINT3 — External interrupt 3 input.

CAP0.0 — Capture input for Timer 0, channel 0.

P1.0 to P1.31

I/O

Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon the pin

function selected via the Pin Connect Block. Pins 0 through 15 of port 1 are

not available.

P1.16

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1.17

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1.18

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1.19

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1.20

TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1.25:16 to

operate as Trace port after reset.

P1.21

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1.22

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1.23

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1.24

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

P1.25

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.26

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bi-directional pin with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1.31:26 to

operate as Debug port after reset.

P1.27

TDO — Test Data out for JTAG interface.

P1.28

TDI — Test Data in for JTAG interface.

P1.29

TCK — Test Clock for JTAG interface.

P1.30

TMS — Test Mode Select for JTAG interface.

P1.31

TRST — Test Reset for JTAG interface.

NC — Pin not connected.

RESET

External Reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

Input to the oscillator circuit and internal clock generator circuits.

Table 3:

Pin description…continued

Symbol

Type

Description

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