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ADA4930-2YCPZ-R7 数据表(PDF) 21 Page - Analog Devices |
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ADA4930-2YCPZ-R7 数据表(HTML) 21 Page - Analog Devices |
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21 / 25 page ![]() Data Sheet ADA4930-1/ADA4930-2 Rev. C | Page 21 of 25 Terminating a Single-Ended Input in a Single-Supply Applications When the application circuit of Figure 50 is powered by a single supply, the common-mode voltage at the amplifier inputs, VP and VN, may have to be raised to comply with the specified input common-mode range. Two methods are available: a dc bias on the source, as shown in Figure 51, or by connecting resistors RCM between each input and the supply, as shown on Figure 54. Input Common-Mode Adjustment with DC Biased Source To drive a 1.8 V ADC with VCM = 1 V, a 3.3 V single supply minimizes the power dissipation of the ADA4930-1/ADA4930-2. The application circuit of Figure 50 on a 3.3 V single supply with a dc bias added to the source is shown in Figure 51. ADA4930 RL VOUT, dm 1.990V p-p 3.3V RS 50Ω RG1 142Ω VP VN RG2 142Ω RF2 301Ω RF1 301Ω VOCM VS 2V p-p VDC RT 64.2 Ω 64.2 Ω 50 Ω Figure 51. Single-Supply, Terminated Single-Ended-to-Differential System with G = 1 To determine the minimum required dc bias, the following steps must be taken: 1. Convert the terminated inputs to their Thevenin equivalents, as shown in the Figure 52 circuit. ADA4930 RL VOUT, dm 1.99V p-p 3.3V VON VOP RTH 28.11Ω RG1 142Ω VP VN RG2 142Ω RF2 301Ω RF1 301Ω VOCM VTH 1.124V p-p VDC-TH RTH 28.11Ω Figure 52. Thevenin Equivalent of Single-Supply Application Circuit 2. Write a nodal equation for VP or VN. ( ) TH DC TH ON TH DC TH P V V V V V V − − − − + + + + + = 28.11 142 301 28.11 142 ) ( 28.11 142 301 28.11 142 TH DC OP TH DC N V V V V − − − + + + + = Recognize that while the ADA4930-1/ADA4930-2 is in its linear operating region, VP and VN are equal. Therefore, both equations in Step 2 give equal results. 3. To comply with the minimum specified input common-mode voltage of 0.3 V at VS = 3.3 V, set the minimum value of VP and VN to 0.3 V. 4. Recognize that VP and VN are at their minimum values when VOP and VS are at their minimum (and therefore VON is at its maximum). Let VPmin = VNmin = 0.3 V, VOCM = VCM = 1 V, VTHmin = −VTH/2 VONmax = VOCM + VOUT,dm/4 and VOPmin = VOCM − VOUT,dm/4 Substitute conditions into the nodal equation for VP and solve for VDC-TH. 0.3 = −1.124/2 + VDC-TH + 0.361 × (1 + 1.99/4 + 1.124/2 – VDC-TH) 0.3 + 0.562 − 0.361 − 0.18 − 0.203 = 0.639 VDC-TH VDC-TH = 0.186 V Or Substitute conditions into the nodal equation for VN and solve for VDC-TH. 0.3 = VDC-TH + 0.361 × (1 − 1.99/4 − VDC-TH) 0.3 – 0.361 + 0.18 = 0.639 × VDC-TH VDC-TH = 0.186 V 5. Converting VDC-TH from its Thevenin equivalent results in V 0.33 0.186 = × + = TH TH S DC R R R V The final application circuit is shown in Figure 53. The additional dc bias of 0.33 V at the inputs ensures that the minimum input common-mode requirements are met when the source signal is bipolar with a 2 V p-p amplitude and VOCM is at 1 V. 3.3V ADA4930 RL VOUT, dm 1.990V p-p RS 50Ω RG1 142Ω RG2 142Ω RF2 301Ω RF1 301Ω VOCM VS 2V p-p RT 64.2Ω 64.2Ω VP VN 50 Ω VDC 0.33V Figure 53. Single-Supply Application Circuit with DC Source Bias |
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