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ST7LITE1 数据表(PDF) 59 Page - STMicroelectronics |
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ST7LITE1 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 131 page  ST7LITE1 59/131 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.4 Low Power Modes 11.2.5 Interrupts Note 1: The CMP and IC events are connected to the same interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Note 2: Only if CK0=1 and CK1=0 (fCOUNTER = fLTIMER) Mode Description SLOW The input frequency is divided by 32 WAIT No effect on AT timer ACTIVE-HALT AT timer halted except if CK0=1, CK1=0 and OVFIE=1 HALT AT timer halted Interrupt Event1) Event Flag Enable Control Bit Exit from Wait Exit from Halt Exit from Active- Halt Overflow Event OVF OVIE Yes No Yes2) IC Event ICF ICIE Yes No No CMP Event CMPF0 CMPIE Yes No No 1 |
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