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STV7620F 数据表(PDF) 7 Page - STMicroelectronics |
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STV7620F 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 16 page ![]() STV7620S/M/F 7/16 4 DATA BUS CONFIGURATION This table describes the position of the first data sampled by the first rising edge of the CLK signal. After 16 clock pulses this data will be shifted to Output 91. F/R Input Data Shift CLK 01 02 03 04 05 06 ... 11 12 13 14 15 16 L A1 A2 A3 A4 A5 A6 Out Out Out Out Out Out 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 For- ward Shift H A1 A2 A3 A4 A5 A6 Out Out Out Out Out Out 91 92 93 94 95 96 85 86 87 88 89 90 79 80 81 82 83 84 73 74 75 76 77 78 67 68 69 70 71 72 61 62 63 64 65 66 31 32 33 34 35 36 25 26 27 28 29 30 19 20 21 22 23 24 13 14 15 16 17 18 07 08 09 10 11 12 01 02 03 04 05 06 Re- verse Shift |
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