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AD9642

Data Sheet

Rev. B | Page 20 of 28

Jitter on the rising edge of the input clock is still of paramount

concern and is not reduced by the duty cycle stabilizer. The duty

cycle control loop does not function for clock rates less than

40 MHz nominally. The loop has a time constant associated

with it that must be considered when the clock rate may change

dynamically. A wait time of 1.5 μs to 5 μs is required after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal. During the time that the loop

is not locked, the DCS loop is bypassed, and internal device timing

is dependent on the duty cycle of the input clock signal. In such

applications, it may be appropriate to disable the duty cycle

stabilizer. In all other applications, enabling the DCS circuit is

recommended to maximize ac performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (fIN) due to jitter (tJ) can be calculated by

SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10

)

(

SNR



]

In the equation, the rms aperture jitter represents the root-

mean-square of all jitter sources, which include the clock input,

the analog input signal, and the ADC aperture jitter specification.

IF undersampling applications are particularly sensitive to jitter,

as shown in Figure 56.

100

1000

INPUT FREQUENCY (MHz)

0.05ps

0.2ps

0.5ps

1ps

1.5ps

MEASURED

Figure 56. AD9642-250 SNR vs. Input Frequency and Jitter

In cases where aperture jitter may affect the dynamic range of the

AD9642, treat the clock input as an analog signal. In addition,

use separate power supplies for the clock drivers and the ADC

output driver to avoid modulating the clock signal with digital

noise. Low jitter, crystal controlled oscillators provide the best

clock sources. If the clock is generated from another type of source

(by gating, dividing, or another method), it should be retimed

by the original clock during the last step.

Refer to the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter, for

more information about jitter performance as it relates to ADCs.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 57, the power dissipated by the AD9642 is

proportional to its sample rate. The data in Figure 57 was taken

using the same operating conditions as those used for the

Typical Performance Characteristics section.

0.05

0.10

0.15

0.20

0.25

0.1

0.2

0.3

0.4

85 100 115 130 145 160 175 190 205 220 235 250

ENCODE FREQUENCY (MSPS)

IAVDD

TOTAL POWER

IDRVDD

Figure 57. AD9642-250 Power and Current vs. Sample Rate

By setting the internal power-down mode bits (Bits[1:0]) in the

power modes register (Address 0x08) to 01, the AD9642 is

placed in power-down mode. In this state, the ADC typically

dissipates 2.5 mW. During power-down, the output drivers are

placed in a high impedance state.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, the wake-up time is related to

the time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. To put the part into standby

mode, set the internal power-down mode bits (Bits[1:0]) in the

power modes register (Address 0x08) to 10. See the Memory

Map section and the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI, for additional details.

DIGITAL OUTPUTS

The AD9642 output drivers can be configured for either ANSI

LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Digital Output Enable Function (OEB)

The AD9642 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled using the SPI

interface. The data outputs can be three-stated by using the

output enable bar bit (Bit 4) in Register 0x14. This OEB

function is not intended for rapid access to the data bus.

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