AD9683 datasheet(4/45 Pages) AD

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Data Sheet

AD9683

Rev. D | Page 3 of 44

Flexible power-down options allow significant power savings,

when desired. Programmable overrange level detection is

supported via the dedicated fast detect pins.

Programming for setup and control is accomplished using a

3-wire SPI-compatible serial interface.

The AD9683 is available in a 32-lead LFCSP and is specified

over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Integrated 14-bit, 170 MSPS/250 MSPS ADC.

2. The configurable JESD204B output block supports lane

rates up to 5 Gbps.

3. An on-chip, phase-locked loop (PLL) allows users to provide a

single ADC sampling clock; the PLL multiplies the ADC

sampling clock to produce the corresponding JESD204B

data rate clock.

4. Support for an optional radio frequency (RF) clock input to

ease system board design.

5. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 400 MHz.

6. Operation from a single 1.8 V power supply.

7. Standard serial port interface (SPI) that supports various

product features and functions, such as controlling the clock

DCS, power-down, test modes, voltage reference mode,

overrange fast detection, and serial output configuration.

AD9683 数据表(PDF) 4 Page - Analog Devices