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AD5171BRJ5-R2 数据表(PDF) 15 Page - Analog Devices |
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AD5171BRJ5-R2 数据表(HTML) 15 Page - Analog Devices |
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15 / 20 page ![]() AD5171 Table 9. SDA Bits Definitions and Descriptions Bit Description Bit Description S P Start Condition. Stop Condition. D5, D4, D3, D2, D1, D0 Data Bits. A Acknowledge. AD0 I2C Device Address Bit. Allows maximum of two AD5171s to be addressed. X Don’t Care. T OTP Programming Bit. Logic 1 programs wiper position permanently. E1, E0 0, 0 0, 1 1, 0 1, 1 OTP Validation Bits. Ready to Program. Test Fuse Not Blown Successfully. (For Factory Setup Checking Purpose Only. Users should not see these combinations). Fatal Error. Try again. Programmed Successfully. No further adjustments possible. I2C Controller Programming Write Bit Pattern Illustrations SDA FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE SCL ACK. BY AD5171 ACK. BY AD5171 ACK. BY AD5171 STOP BY MASTER START BY MASTER 0 1 1 0 11 0 AD0 R/W 0 X X X X X X X X XD5 D4 D3 D2 D1 D0 9 1 9 1 9 Figure 36. Writing to the RDAC Register SDA FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE SCL ACK. BY AD5171 ACK. BY AD5171 ACK. BY AD5171 STOP BY MASTER START BY MASTER 0 1 1 0 11 0 AD0 R/W 1X XX X X X X X X D5 D4D3 D2D1 D0 9 1 9 1 9 Figure 37. Activating One-Time Programming Read Bit Pattern Illustration SDA FRAME 1 SLAVE ADDRESS BYTE FRAME 2 RDAC REGISTER SCL ACK. BY AD5171 NO ACK. BY MASTER STOP BY MASTER START BY MASTER 0 1 1 0 11 0 AD0 E1 E0 D5 D4 D3 D2 D1 D0 91 9 R/W Figure 38. Reading Data from RDAC Register For users who prefer to use external controllers, the AD5171 can be controlled via an I2C compatible serial bus and is connected to this bus as slave device. Referring to Figure 36, Figure 37, and Figure 38, the 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when SDA from high-to-low while SCL is high (Figure 36 and Figure 37). The following byte is the slave address byte, which consists of the 6 MSBs as a slave address defined as 010110. The next bit is AD0, which is an I2C device address bit. Depending on the states of their AD0 bits, two AD5171 can be addressed on the same bus (Figure 39). The last LSB is the R/W bit, which determines whether data will be read from or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line goes low during the 9th clock pulse (this is termed the Acknowledge bit). At Rev. PrC | Page 15 of 20 Preliminary Technical Data |
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