AD6652BC datasheet(38/76 Pages) AD

38 / 76 page

AD6652

Rev. 0 | Page 38 of 76

, one tap for I and one tap for Q

RAM COEFFICIENT FILTER

The final signal processing stage is a sum-of-products decimat-

ing filter with programmable coefficients. A simplified block

diagram is shown in Figure 49. The data memories I-RAM an

Q-RAM store the 160 most recent complex samples from th

previous filter stage with 20-bit resolution. The coefficient

memory, CMEM, stores up to 256 coefficients with 20-bit

resolution. On every CLK cycle

are calculated using the same coefficients. The RCF output

consists of 24 bits of I data and 24 bits of Q data.

160

× 20B

I-RAM

I IN

I OUT

256

× 20B

C-RAM

160

× 20B

Q-RAM

Q IN

Q OUT

Figure 49. RAM Coefficient Filter Block Diagram

RCF DECIMATION REGISTER

Use each RCF channel to decimate the data rate. The decima-

tion register is an 8-bit register that can decimate from 1 to 256

The RCF decimation is stored in 0xA0 in the form of M

application, two RCF filters would be processing the same data

RCF

−

The input rate to the RCF is fSAMP5.

RCF DECIMATION PHASE

Use the RCF decimation phase to synchronize multiple filters

within a chip. This is useful when using multiple channels

within the AD6652 to implement a polyphase filter, requiring

that the resources of several filters be paralleled. In such an

from the CIC5. However, each filter is delayed by one-half th

decimation rate, thus creating a 180° phase difference between

the two halves. The AD6652 filter channel uses the value stored

in this register to preload the RCF counter. Therefore, instead

starting from 0, the counter is loaded with this value, thus

creating an offset in the processing that should be equivalent to

the required processing delay. This data is stored in 0xA1 as an

8-bit number.

RCF FILTER LENGTH

The maximum number of taps this filter can calculate, Ntaps, is

given by the following equation. The value Ntaps − 1 is written to

the channel register within the AD6652 at address 0xA

⎟⎟

⎠

⎝

SAMP

here

min indicates th

⎞

⎜

160

min

RCF

taps

at Ntaps is the lesser of the two values,

the

ents need not be symmetric, and the

coefficient length, Ntaps, can be e

r odd. If the coefficients

are symmetric, th

ponse must be

written into the coefficient RAM.

ts is only 128 words

es,

data from the CIC5 into a 160 × 40 RAM.

ficient address RCFOFF + Ntaps − 1 is reached.

⎜

⎛

≤

CLK

separated by the comma, that appear within the brackets.

The RCF coefficients are located in addresses 0x00 to 0x7F and

are interpreted as 20-bit twos complement numbers. When

writing the coefficient RAM, the lower addresses are multiplied

by relatively older data from the CIC5, and the higher coeffi-

cient addresses are multiplied by relatively newer data from

CIC5. The coeffici

ven o

en both sides of the impulse res

Although the base memory for coefficien

long, the actual length is 256 words long. There are two pag

each of 128 words long. The page is selected by Bit 8 of 0xA4.

Although this data must be written in pages, the internal core

handles filters that exceed the length of 128 taps. Therefore, the

full length of the data RAM can be used as the filter length

(160 taps).

The RCF stores the

160 × 20 is assigned to I data and 160 × 20 is assigned to Q data.

The RCF uses the RAM as a circular buffer, so that it is difficult

to know in which address a particular data element is stored.

When the RCF calculates a filter output, it starts by multiplying

the oldest value in the data RAM by the first coefficient, which

is pointed to by the RCF coefficient offset register (0xA3). This

value is accumulated with the products of newer data words

multiplied by the subsequent locations in the coefficient RAM

until the coef

Table 16. Three-Tap Filter

Coefficient Address

Impulse Response

Data

h(0)

N(0) oldest

h(1)

N(1)

2 = (Ntaps − 1)

h(2)

N(2) newest

The RCF coefficient offset register has two purposes. The ma

purpose of this register is for rapid filter changes, by allowin

multiple filters to be loaded into memory and then selected

his

simply by changing the offset as a pointer. The other use of t

desired filter length is padded with zeros on the ends, then the

starting point can be adjusted to form slight delays in when the

filter is computed with reference to the high speed clock. This

allows for vernier adjustment of the symbol timing. Course

adjustments can be made with the RCF decimation phase.

The output rate of this filter is determined by the output rate o

the CIC5 stage and MRCF, as follows:

RCF

SAMP

SAMPR

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