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AD5171BRJ10-R2 数据表(PDF) 13 Page - Analog Devices |
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AD5171BRJ10-R2 数据表(HTML) 13 Page - Analog Devices |
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13 / 20 page ![]() AD5171 TERMINAL VOLTAGE OPERATING RANGE There are also ESD protection diodes between VDD and the RDAC terminals. The VDD of AD5171 therefore defines their voltage boundary conditions, see Figure 29. Supply signals present on terminals A, B, and W that exceed VDD will be clamped by the internal forward-biased diodes and should be avoided. GND A W B VDD Figure 29. Maximum Terminal Voltages Set by VDD POWER-UP/POWER-DOWN SEQUENCES Similarly, because of the ESD protection diodes, it is important to power VDD first before applying any voltages to terminals A, B, and W. Otherwise, the diode will be forward-biased such that VDD will be powered unintentionally and may affect the rest of the users’ circuits. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD. Similarly, VDD should be powered down last. POWER SUPPLY CONSIDERATIONS To minimize the package pin count, both the one-time programming and normal operating voltages are applied to the same VDD terminal of the AD5171. The AD5171 employs fuse link technology that requires 6 V to blow the internal fuses to achieve a given setting. On the other hand, it operates at 2.7 V to 5.5 V once the programming is complete. Such dual voltage requires isolation between supplies. The fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 6 V and be able to handle 400 ms and 100 mA of transient current for one-time programming. Once programming is complete, the 6 V supply must be removed to allow normal operation of 2.7 V to 5.5 V. Figure 30 shows the simplest implementation using a jumper. This approach saves one voltage supply, but draws additional current and requires manual configuration. AD5171 VDD C2 0.1 µF 5V CONNECT J1 HERE FOR OTP C1 1 µF J1 R1 50k Ω R2 250k Ω 6V CONNECT J1 HERE AFTER OTP Figure 30. Power Supply Requirement An alternate approach in 3.5 V to 5.5 V systems adds a signal diode between the system supply and the OPT supply for isolation, as shown in Figure 31. AD5171 VDD C2 0.1 µF APPLY FOR OTP ONLY C1 10 µF D1 3.5V–5.5V 6V Figure 31. Isolating the 6 V OPT Supply from the 3.5V to 5.5 V Normal Operating Supply. The 6 V supply must be removed once OPT is complete. AD5171 VDD C2 0.1 µF APPLY FOR OTP ONLY C1 10 µF 10k Ω 2.7V 6V P1 P2 R1 P1 = P2 = FDV302P, NDS0610 Figure 32. Isolating the 6 V OPT Supply from the 2.7 V Normal Operating Supply. The 6 V supply must be removed once OPT is complete. For users who operate their systems at 2.7 V, it is recommended to use the bi-directional low-threshold P-Ch MOSFETs for the supplies isolation. As shown in Figure 32 assumes the 2.7 V system voltage is applied first but not the 6 V. The gates of P1 are P2 are pulled to ground, which turns on P1 and subse- quently P2. As a result, VDD of AD5171 becomes 2.7 V minus a few tenths of mV drop across P1 and P2. When the AD5171 setting is found, the factory tester applies the 6 V to VDD and also to the gates of P1 and P2 to turn them off. While the OTP command is executing at this time to program AD5171, the 2.7 V source is therefore protected. Once the OTP is complete, the tester withdraws the 6 V, and AD5171 setting is permanently fixed. Rev. PrC | Page 13 of 20 Preliminary Technical Data |
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