Dual High Speed PECL Comparators

ADCMP561/ADCMP562

Rev. A

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FEATURES

Differential PECL compatible outputs

700 ps propagation delay input to output

75 ps propagation delay dispersion

Input common-mode range: –2.0 V to +3.0 V

Robust input protection

Differential latch control

Internal latch pull-up resistors

Power supply rejection greater than 85 dB

700 ps minimum pulse width

1.5 GHz equivalent input rise time bandwidth

Typical output rise/fall time of 500 ps

ESD protection > 4kV HBM, >200V MM

Programmable hysteresis

APPLICATIONS

Automatic test equipment

High speed instrumentation

Scope and logic analyzer front ends

Window comparators

High speed line receivers

Threshold detection

Peak detection

High speed triggers

Patient diagnostics

Disk drive read channel detection

Hand-held test instruments

Zero-crossing detectors

Line receivers and signal restoration

Clock drivers

FUNCTIONAL BLOCK DIAGRAM

HYS*

*ADCMP562 ONLY

NONINVERTING

INPUT

INVERTING

INPUT

LATCH ENABLE

INPUT

Q OUTPUT

LATCH ENABLE

INPUT

Q OUTPUT

ADCMP561/

ADCMP562

Figure 1.

ADCMP561

TOP VIEW

(Not to Scale)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

–INA

+INA

QA

QA

LEA

LEA

–INB

+INB

QB

QB

GND

LEB

LEB

ADCMP562

TOP VIEW

(Not to Scale)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

–INA

QA

QA

LEA

LEA

+INA

HYSA

–INB

QB

QB

GND

LEB

LEB

+INB

HYSB

Figure 2. ADCMP561 16-Lead QSOP

Figure 3. ADCMP562 20-Lead QSOP

GENERAL DESCRIPTION

The ADCMP561/ADCMP562 are high speed comparators

fabricated on Analog Devices’ proprietary XFCB process. The

devices feature a 700 ps propagation delay with less than 75 ps

overdrive dispersion. Dispersion, a measure of the difference in

propagation delay under differing overdrive conditions, is a

particularly important characteristic of comparators. A separate

programmable hysteresis pin is available on the ADCMP562.

A differential input stage permits consistent propagation delay

with a wide variety of signals in the common-mode range from

−2.0 V to +3.0 V. Outputs are complementary digital signals that

are fully compatible with PECL 10 K and 10 KH logic families.

The outputs provide sufficient drive current to directly drive

input, which is included, permits tracking, track-and-hold, or

sample-and-hold modes of operation. The latch input pins

contain internal pull-ups that set the latch in tracking mode

when left open.

The ADCMP561/ADCMP562 are specified over the industrial

temperature range (−40°C to +85°C).