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N+1

N+2

N–1

12 CYCLES

N

VIN

CLK+

CLK–

DX

DCO+

DCO–

N-12

N-11

N-1

N

Figure 3. CMOS Timing Diagram

EXPLANATION OF TEST LEVELS

Test Level

Definitions

I

100% production tested.

II

100% production tested at 25°C and sample tested at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.