Current Limiting (CS, CO and

VOUT)

Current limiting is implemented through the current sense

amplifier as illustrated in Figure 6. The current sense ampli-

fier monitors the inductor current that flows through a sense

resistor connected between CS and VOUT. The voltage gain

of the current sense amplifier is nominally equal to 16. The

output of current sense signal is shifted by 1.27V to produce

the internal CV reference signal. The CV signal drives a

current limit amplifier with nominal transconductance of

16mA/V. The current limit amplifier has an open drain (sink

only) output stage and its output pin CO is typically con-

nected to the COMP pin. During normal operation, the volt-

age error amplifier controls the COMP pin voltage which

adjusts the PWM duty cycle by varying the internal CRMIX

level (Figure 4). However, when the current sense input

voltage V

down on COMP through the CO pin. Pulling COMP low

reduces the CRMIX signal below the CV signal level. When

CRMIX does not exceed the CV signal, the PWM compara-

tor inhibits output pulses until the CRMIX signal increases to

a normal operating level.

A current limit fold-back feature is provided by the LM5115 to

reduce the peak output current delivered to a shorted load.

When the common mode input voltage to the current sense

amplifier (CS and VOUT pins) falls below 2V, the current limit

threshold is reduced from the normal level. At common mode

When VOUT is reduced to 0V the current limit threshold

drops to 36mV to reduce stress on the inductor and power

MOSFETs.

Negative Current Limit

When inductor current flows from the regulator output

through the low side MOSFET, the input to the current sense

comparator becomes negative. The intent of the negative

current comparator is to protect the low side MOSFET from

excessive currents. Negative current can lead to large nega-

tive voltage spikes on the output at turn off which can dam-

age circuitry powered by the output. The negative current

comparator threshold is sufficiently negative to allow induc-

tor current to reverse at no load or light load conditions. It is

not intended to support discontinuous conduction mode with

diode emulation by the low side MOSFET. The negative

current comparator shown illustrated in Figure 6 monitors

the CV signal and compares this signal to a fixed 1V thresh-

old. This corresponds to a negative V

and VOUT of -17mV. The negative current limit comparator

turns off the low side MOSFET for the remainder of the cycle

when the V

Gate Drivers Outputs (HO & LO)

The LM5115 provides two gate driver outputs, the floating

high side gate driver HO and the synchronous rectifier low

side driver LO. The low side driver is powered directly by the

VCC regulator. The high side gate driver is powered from a

bootstrap capacitor connected between HB and HS. An

external diode connected between VCC and HB charges the

bootstrap capacitor when the HS is low. When the high side

MOSFET is turned on, HB rises with HS to a peak voltage

equal to VCC + V

external bootstrap diode. Both output drivers have adaptive

dead-time control to avoid shoot through currents. The adap-

tive dead-time control circuit monitors the state of each

driver to ensure that the opposing MOSFET is turned off

before the other is turned on. The HB and VCC capacitors

should be placed close to the pins of the LM5115 to minimize

20134916

FIGURE 7. Voltage Sensing and Feedback

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