SCANSTA111SM datasheet(21/29 Pages) NSC

21 / 29 page

Special Features (Continued)

•

Number/Type of GPIO bits: The STA111 has both dedi-

cated and shared GPIO (General Purpose I/O). Each

dedicated group of GPIO bits supports from 0 to 4 dedi-

cated inputs and 0 to 4 dedicated outputs. There are

provisions for specifying the default (power-up) value.

TMS

(0-n), TDO(0-n) and TDI(0-n) are also dual purpose

pins functioning as LSP or GPIO. TMS

n and TDOn are

outputs, TDI

n is an input in the GPIO mode.

Throught this datasheet, notations exist to clarify the differ-

ences between features available on the Silicon version and

the HDL version.

KNOWN POWER-UP STATE

The STA111 has a known power-up condition. This is the

same state that the device is in after a TRST reset. This

happens at power-up without the presence of a TCK

Reset can also occur via a 5 TMS high reset or a SOFTRE-

SET command.

POWER-OFF HIGH IMPEDANCE INPUTS AND

OUTPUTS

The STA111 backplane test port features power-off high

impedance inputs and outputs.

The TDI

B, TMSB, and TRSTB inputs have a 25K

Ω pull-up

resistor and no ESD clamp diode (ESD is controlled with an

alternate method). When the device is power-off (V

DD float-

ing), these inputs appear to be a capacitive load to ground.

When V

DD = 0V (i.e.; not floating but tied to VSS) these inputs

appear to be capacitive with the pull-up to ground.

The TCK

B input has no pull-up resistor and no ESD clamp

diode (ESD is controlled with an alternate method). When

the device is power-off (V

DD floating), the input appears to be

a capacitive load to ground. When V

DD = 0V (i.e.; not floating

but tied to V

SS) the input appears to be a capacitive load to

ground.

When the device is power-off (V

DD = 0V or floating), the

TDO

B output appears to be a capacitive load.

Refer to the device IBIS model on our website for more

details

about

the

I/O

characteristics

http://

www.national.com/appinfo/scan/ibis.html.

TRST

B: Assertion of TRSTB will return the device back to its

known power-up state.

TRST

n: TRSTn is an output on the LSP side of the STA111.

While the LSP state-machine (level 2 protocol) is in the

Parked-TLR state the TRST

n pin will be driven low. In all

other states the TRST

n pin will be driven high.

PHYSICAL LAYER CHANGES

TRIST for TDO

B and TDOn are signals for enabling an

external buffer circuit between the ’STA111 and the

backplane/LSP. This would allow, for example, a CMOS-to-

LVDS converter to drive an LVDS JTAG backplane test bus.

These signals are always driving. A seperate TRIST is pro-

vided for each LSP to report a TRI-STATE on TDO when the

LSP is not in a shift state.

SVF DRIVEN, SELF-CHECKING TEST BENCH

The STA111 consists of 3 types of pins, dot1 backplane pins,

dot1 LSP pins and support pins. The command interpreter of

the test bench is able to translate a limited set of SVF

commands to the dot1 backplane pins. The SVF shift com-

mands contain both the stimulus (TDI

B) and expected re-

sponse (TDO

B).

The interpreter is able to parse the following commands:

ENDDR, ENDIR, RUNTEST, SDR, SIR, STATE, TRST.

PASS-THROUGH PINS

Each LSP may selectively have two pass-through pins. The

pair of pass-through pins consist of an input (A

n) and an

output (Y

n). The LSP pass-through output (Yn) drives the

level being received by the backplane pass-through input

B). Conversly, the level on the LSP pass-through input (An)

drives the backplane pass-through output (Y

B).

The Pass-through pins are available only when a single LSP

is selected. For each LSP these pins will be enabled when

the level 2 protocol state-machine is not in the Parked-TLR

state. When not enabled they are TRI-STATED.

LSP GATING

While the LSP state-machine (level 2 protocol) is in the

Parked-TLR state, the four LSP signals shall be controlled

as shown in Table 14 below. Upon entry into the Parked-TLR

state (power-up, reset, PARKTLR or GOTOWAIT) a counter

in the LSP state-machine allows 512 TCK

B clock pulses to

occur on TCK

n before gating. Once gated, TCKn will drive a

logic 0.

Letting 512 TCK

B pulses pass through to TCKn allows a five

high TMS reset to occur on over 100 levels of hierarchy

before the STA111 gates TCK

n (for power saving in a free-

running clock system).

TABLE 14. Gated LSP Drive States

LSP

Connection

Drive State

TDO

Pull-up resistor to provide a weak HIGH

TMS

Pull-up resistor to provide a weak HIGH

TDI

Pull-up resistor to provide a weak HIGH

TCK

B for 512 pulses, then gated LOW

The STA111 does not require that any clock pulses are

received on TCK

B while in the Parked-TLR state.

Setting Bit 3 of Mode Register

0 to 1 gates TCKn when in the

Parked-RTI,

Parked-Pause-DR

and

Parked-Pause-IR

states. Default is free-running (bit 3 = 0). The value stored in

bit 3 of Mode Register

0 does not effect the requirement of

512 clock pulses before gating TCK

n in the Parked-TLR

state. (See section on Mode Register

0).

IEEE 1149.4 SUPPORT

The STA111 provides support for a switched analog bus.

Each

LSP

has

unparked-TLR

notification

(LSP_ACTIVE

(0-2)) which is low (0) when the LSP is in

Parked-TLR and high (1) otherwise. This signal can be used

to enable/disable analog switches external to the STA111.

GPIO CONNECTIONS

General Purpose I/O (GPIO) pins are registered inputs and

outputs that are parameterized in the HDL. The two types of

GPIOs than can be used in the STA111 are described in the

next two sections.

DEDICATED: Each LSP supports up to four (4) dedicated

inputs and up to four (4) dedicated outputs. These are sep-

erate, dedicated GPIO signals controlled by dedicated GPIO

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