Philips Semiconductors

Product specification

SCN2652/SCN68652

Multi-protocol communications controller (MPCC)

1995 May 01

21

RECEIVE END OF MESSAGE

RxC

RxDA

DBEN

(8-BIT)

READ

DATA

READ

STATUS

RxE2

RxA3

NOTES:

1.

which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status.

2.

RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).

3.

RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped.

RxSA1

S/F

SD00072

Figure 17. Timing Diagrams (cont.)

TYPICAL APPLICATIONS

SCN2652 MPCC MICROPROCESSOR INTERFACE

NOTES:

1.

Possible

µP interrupt requests are: RxDA RxSA TxBE TxU

2.

Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn

around control.

3.

Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa.

4.

RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low.

5.

Corresponding high and low order bits of DB must be OR tied.

RESET

CLOCK

8-BIT

µP

Φ

DATA BUS

ADDRESS CONTROL

TS BUFFER

MODEM

CONTROL

LOGIC

STATUS

MPCC

SCN2652

DB0–DB7

A2–A0, R/W DBEN CE

“1”

BYTE

RxE

TxE

DCD

CTS

LR

TxC

SYNCHRO-

NOUS

MODEM

LR

RxC

LD

TxSO

LR

RxSI

RTS, CTS,

DTR, DSR,

DCD

RESET

SD00073

Figure 18. Typical Applications