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Preliminary Technical Data

AD9736/AD9735/AD9734

Rev. PrJ | Page 27 of 42

AD9736 DIGITAL BUILT-IN SELF TEST

BIST may be used to validate data transfer to the AD9736 in

addition to final ATE device verification. There are 4 BIST

signatures that can be read back using Registers 18-21 based on the

setting of the BIST selection bits (REG17, bits 7:6) as shown in

Table 12.

SEL<1>

SEL<0>

1 - LVDS Phase 1

2 - LVDS Phase 2

3 - SYNC Phase 1

4 - SYNC Phase 2

Table 12. BIST Selection Bits

The BIST signature returned from the AD9736 will depend on the

input DATA during the test. Since the filters in the DAC have

memory, it is important to put the correct idle value on the DATA

inputs to flush the memory prior to reading the BIST signature.

Placing the idle value on the data inputs also allows the BIST to be

setup while the DAC clock is running. The idle value should be all

zeroes in unsigned mode (0x0000) and all zeroes except for the

MSB in two’s complement mode (0x2000).

The BIST consists of two stages; the first stage is after the LVDS

receiver and the second stage is after the FIFO stage. The first BIST

stage verifies correct sampling of the data from the LVDS bus while

the second BIST stage verifies correct synchronization between the

DAC_CLK domain and the DATA_CLK domain. The BIST vector

is generated using 32 bit LFSR signature logic. Since the internal

architecture is a two bus parallel system there are two 32-bit LFSR

signature logic blocks on the both the LVDS and SYNC blocks.

Figure 30 shows where the LVDS and SYNC phases are located.

Figure 30. Block Diagram Showing LVDS and SYNC Phase 1 and Phase 2

BIST OPERATION

The internal signature generator processes the input data to create

the BIST signatures. An external program which implements the

same algorithm may be used to generate the expected signature for

comparison. A Matlab routine can be provided upon request to

perform this function.

Clock the test vector in as described below and compare the

signature register values to the expected value to verify correct

operation and input data capture.

With all clocks running:

Apply the idle vector to the data inputs (0x0000 if

unsigned, 0x2000 if two's complement) for 1024 clocks,

Set LVDS_EN (REG17, bit 2) and SYNC_EN (REG17, bit

1) high,

Set CLEAR (REG17, bit 0) high,

Set CLEAR low to clear the BIST signature register,

Clock the BIST vector into the LVDS data inputs,

After the BIST vector is complete, return the inputs to the

idle vector value,

Set LVDS_EN (REG17, bit 2) and SYNC_EN (REG17, bit

1) low,

Set the desired SEL<1:0> bits and read back the four

BIST signature registers (REG18, 19, 20 and 21).

When the DAC is in 1x mode, the signature at SYNC BIST, Phase 1

should equal the signature at LVDS BIST, Phase 1. The same is

true for Phase 2. BIST does not support 2x mode.

LVDS

Figure 24

DB<13:0>

DATACLK_IN

LVDS

BIST

PH1

LVDS

BIST

PH2

SYNC

BIST

PH1

SYNC

BIST

PH2

SYNC Logic

DAC

SPI Port

FIFO

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