AD5251EVAL datasheet(21/28 Pages) AD

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AD5251/AD5252

Rev. 0 | Page 21 of 28

DIGITAL INPUT/OUTPUT CONFIGURATION

SDA is a digital input/output with an open-drain MOSFET that

requires a pull-up resistor for proper communication. On the

other hand, SCL and WP are digital inputs for which pull-up

resistors are recommended to minimize the MOSFETs cross

conduction current when the driving signals are lower than

VDD. SCL and WP have ESD protection diodes, as shown in

Figure 35 and Figure 36.

WP can be permanently tied to VDD without a pull-up resistor if

the write-protect feature is not used. If WP is left floating, an

internal current source pulls it low to enable write-protect. In

applications where the device is not being programmed on a

frequent basis, this allows the part to default to write-protect

after any one-time factory programming or field calibration

without the use of an on board pull-down resistor. Because

there are protection diodes on all these inputs, their signal levels

must not be greater than VDD to prevent forward biasing of the

diodes.

GND

SCL

VDD

Figure 35. SCL Digital Input

GND

INPUTS

VDD

Figure 36. Equivalent WP Digital Input

MULTIPLE DEVICES ON ONE BUS

The AD5251/AD5252 are equipped with two addressing pins,

AD1 and AD0, that allow up to four AD5251/AD5252s to be

operated on one I2C bus. To achieve this result, the states of

AD1 and AD0 on each device must first be defined. An example

is shown in Table 12 and Figure 37. In I2C programming, each

device is issued a different slave address—01011(AD1)(AD0)—

to complete the addressing.

Table 12. Multiple Devices Addressing

AD1

AD0

Device Addressed

VDD

+5V

VDD

AD0

AD1

SDA SCL

MASTER

AD0

AD1

SDA SCL

AD0

AD1

SDA SCL

AD0

AD1

SDA

SCL

Figure 37. Multiple AD5251/AD5252s on a Single Bus

TERMINAL VOLTAGE OPERATION RANGE

The AD5251/AD5252 are designed with internal ESD diodes

for protection; these diodes also set the boundary of the

terminal operating voltages. Positive signals present on

Terminal A, B, or W that exceed VDD are clamped by the

forward biased diode. Similarly, negative signals on Terminal A,

B, or W that are more negative than VSS are also clamped (see

Figure 38). In practice, users should not operate VAB, VWA, and

VWB to be higher than the voltage across VDD to VSS, but VAB,

VWA, and VWB have no polarity constraint.

VSS

VDD

Figure 38. Maximum Terminal Voltages Set by VDD and VSS

POWER-UP AND POWER-DOWN SEQUENCES

Because the ESD protection diodes limit the voltage compliance

at terminals A, B, and W (see Figure 38), it is important to

power-on VDD/VSS before applying any voltage to Terminals A,

B, and W. Otherwise, the diodes are forward-biased such that

VDD/VSS are powered unintentionally and may affect the rest of

the user’s circuit. Similarly, VDD/VSS should be powered down

last. The ideal power-up sequence is in the following order:

GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of

powering VA, VB, VW, and the digital inputs is not important, as

long as they are powered after VDD/VSS.

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