M24C08-RMB6TSLASHW datasheet(8/29 Pages) STMICROELECTRONICS

8 / 29 page

M24C16, M24C08, M24C04, M24C02, M24C01

8/29

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

Write Operations

Following a Start condition the bus master sends

a Device Select Code with the RW bit reset to 0.

The device acknowledges this, as shown in Figure

7., and waits for an address byte. The device re-

sponds to the address byte with an acknowledge

bit, and then waits for the data byte.

When the bus master generates a Stop condition

immediately after the Ack bit (in the “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Serial Data (SDA)

and Serial Clock (SCL) are ignored, and the de-

vice does not respond to any requests.

Byte Write

After the Device Select code and the address byte,

the bus master sends one data byte. If the ad-

dressed location is Write-protected, by Write Con-

trol (WC) being driven High (during the period from

the Start condition until the end of the address

byte), the device replies to the data byte with

NoAck, as shown in Figure 6., and the location is

not modified. If, instead, the addressed location is

not Write-protected, the device replies with Ack.

The bus master terminates the transfer by gener-

ating a Stop condition, as shown in Figure 7..

Page Write

The Page Write mode allows up to 16 bytes to be

written in a single Write cycle, provided that they

are all located in the same page in the memory:

that is, the most significant memory address bits

are the same. If more bytes are sent than will fit up

to the end of the page, a condition known as ‘roll-

over’ occurs. This should be avoided, as data

starts to become overwritten in an implementation

dependent way.

The bus master sends from 1 to 16 bytes of data,

each of which is acknowledged by the device if

Write Control (WC) is Low. If the addressed loca-

tion is Write-protected, by Write Control (WC) be-

ing driven High (during the period from the Start

Byte Write

DEV SEL

BYTE ADDR

DATA IN

Page Write

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

DATA IN 3

AI02803C

Page Write

(cont'd)

WC (cont'd)

DATA IN N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

M24C08-RMB6T/W 数据表(PDF) 8 Page - STMicroelectronics

M24C08-RMB6T/W 数据表(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载

链接网址

M24C08-RMB6T/W 数据表(PDF) 8 Page - STMicroelectronics

M24C08-RMB6T/W 数据表(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表 下载

链接网址

数据表下载