AD6600STSLASHPCB datasheet(18/25 Pages) AD

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REV. 0

AD6600

–17–

Table II. Selecting AD6600 Operating Mode

Output vs. Encode Clock

Mode

A_SEL

B_SEL

n+1

n+2

n+3

Dual: A/B

Single: A

Single: B

Not Valid

––

–

A_SEL and B_SEL are not logic inputs and should be tied

directly to ground or analog VCC (5 V analog).

In dual channel mode, the AB_OUT signal indicates which

input is currently available on the digital output. When the

AB_OUT is 1, the digital output is the digitized version of

Channel A. Likewise, when AB_OUT is 0, the Channel B is

available on the digital output (Table III).

Table III. AB_OUT for Dual Channel Operation

Output Data vs. Encode Clock

A_SEL and B_SEL = 1

n+1

n+2

n+3

D[10:0], RSSI[2:0]

AB_OUT

1010

Data Output Stage

The output stage provides data in the form of mantissa, D[10:0],

and exponent, RSSI[2:0], where D[10:0] represents the output

of the 11-bit ADC coded as two’s complement, and RSSI[2:0]

represents the gain-range setting coded in offset binary. Table

IV shows the nominal gain-ranges for a nominal 2 V p-p differ-

ential full-scale input. Keep in mind that the actual full-scale

input voltage and power will vary with input frequency.

Table IV. Interpreting the RSSI Bits

Differential

RSSI [2:0]

Analog Input Voltage

Decimal

Attenuation

(V p-p)

Binary

Equiv.

or Gain (dB)

0.5 < VIN

101

–12

0.25 < VIN < 0.5

100

–6

0.125 < VIN < 0.25

011

0.0625 < VIN < 0.125

010

0.03125 < VIN < 0.0625

001

+12

VIN < 0.03125

000

+18

The digital processing chip which follows the AD6600 can com-

bine the 11 bits of two’s complement data with the 3 RSSI bits

to form a 16-bit equivalent output word. Table V explains how

the RSSI data can be interpreted when using a PLD or ASIC.

Basically, the circuit performs right shifts of the data depending

on the RSSI word. This can also be performed in software using

the following pseudo code fragment:

r0 = dm (rssi);

r2 = 5;

r0 = r2–r0;

r1 = dm (adc); (11 bits, MSB justified into DSP word)

rshift r1, r0; (arithmetic shift to extend the sign bit)

The result of the shifted data is a 16-bit fixed-point word that

can be used as any normal 16-bit word.

Table V. 16-Bit, Fixed-Point Data Format

16-Bit Data

Corresponds to a

RSSI

11-Bit Word

Format

Shift Right of

101

DATA

× 32

100

DATA

× 16

011

DATA

× 83

010

DATA

× 42

001

DATA

× 21

000

DATA

× 10

When mated with the AD6620, Digital Receive Processor Chip,

the AD6600 floating point data (mantissa + exponent) is automati-

cally converted to 16-bit two’s complement format by the AD6620.

APPLYING THE AD6600

Encoding the AD6600

The AD6600 encode signal must be a high quality, extremely

low phase noise source to prevent degradation of performance.

Digitizing high frequency signals (IF range 70 MHz–250 MHz)

places a premium on encode clock phase noise. SNR perfor-

mance can easily degrade by 3 dB–4 dB with 70 MHz input

signals when using a high-jitter clock source. At higher IFs (up

to 250 MHz), and with high-jitter clock sources, the higher

slew rates of the input signals reduce performance even further.

See AN-501, Aperture Uncertainty and ADC System Performance

for complete details.

For optimum performance, the AD6600 must be clocked differ-

entially. The encode signal is usually ac-coupled into the ENC

and

ENC pins via a transformer or capacitors. These pins are

biased internally and require no additional bias.

Figure 18 shows one preferred method for clocking the AD6600.

The sine source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD6600 to approximately 0.8 V p-p differential. This

helps prevent the larger voltage swings of the clock from feeding

through to other portions of the AD6600, and limits the noise

presented to the encode inputs. A crystal clock oscillator can

also be used to drive the RF transformer if an appropriate

limiting resistor (typically 100

Ω) is placed in the series with

the primary.

ENCODE

AD6600

T1–1T

5082–2810

DIODES

SINE

SOURCE

100

Figure 18. Transformer-Coupled Sine Source

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