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AD6650

Rev. A | Page 40 of 44

0x0A: Coarse DC Correction Control Register [3:0]

Address 0xA is the coarse dc correction control register. It is

used to enable the coarse correction with Bit 0 and to initiate

calibrations on Channel A and/or Channel B. Bit 3 and Bit 2 of

this register can be used to initiate coarse calibrations when the

device is running and can be used in conjunction with an

external switch if desired. Bit 1 is used to activate the internal

pseudorandom noise generator, which is useful for looking at

the digital filter response and performing the built-in self-test.

Table 23. Coarse DC Correction Control Functions

Bit No.

Description

Calibrate B

Calibrate A

PN_EN

CDCC enable

0xB: Fine DC Correction Filter [19:0]

The fine dc correction block is used to provide a good dc

correction for small signals that are under the range of the AGC

loop. Address 0xB has four parameters.

Table 24. Fine DC Correction Filter Functions

Bits

Description

19 to 13

Upper threshold

12 to 8

Lower threshold

7 to 3

Minimum period

Bypass

Interpolator enable

Freeze

Bit 19 to Bit 13

The upper threshold disables the fine dc correction algorithm for

large input signals that could potentially contain significant dc

content from the modulated data. This should be set below the

range of the AGC loop, which is equal to the requested level of

−36 dB. It should also be set above the uncorrected dc level so that

the fine DCC is guaranteed to range.

The upper threshold should be set low enough so that the dc

content is not estimated while the loop is ranging because the

changing gain distorts the estimate. Setting the upper threshold

lower also decreases effects from dc content in the signal such

as dc offset from modulated data with high correlations or

mobiles with LO feedthrough.

It is equally important not to set the upper threshold too low.

If the upper threshold is set so low that the desired signal is

consistently higher than this threshold, a new dc estimate, which

is necessary to compensate for power supply or temperature

drifts, will not occur. Therefore, a thorough understanding of

the signal statistics for the application is required.

As a guideline, the upper threshold should be set between

−40 dBFS and −70 dBFS. If it is set below −72 dBFS, the

uncorrected dc offset from the analog front end and coarse

correction can increase the effective minimum period because

the peak detectors in the fine dc correction block ranges off the

dc content as well as the signal of interest.

Bit 12 to Bit 8

The lower threshold determines where the minimum integration

period is used. When the peak of the input to the fine dc

correction block is lower than this level, the accumulators

average 2Min_period samples at the output rate (1 or 2 samples/symbol).

When the peak of the signal increases above this, the integration

periods increase by a factor of 4 for every 6 dB that the signal

power increases.

It should be noted that any dc content left after the coarse

correction can be seen by the fine dc correction peak detector

and causes the integration period to change. For example, if the

lower threshold is −96 dBFS and the dc content is −78 dBFS, the

signal is at least 18 dB larger; therefore, the integration period is

at least 64× (that is, 418/6) the minimum period.

The lower threshold can be set near the upper threshold to

provide a constant integration period of 2Min_period if desired.

Bit 7 to Bit 3

This interval is equal to 2Min_period. The minimum period

determines the integration period when the peak signal power

into the fine dc correction block is less than the lower threshold.

This can be used in combination with the lower threshold to

make sure there is enough integration to estimate the dc for

small signals.

If Min_period is 12, the period of integration for a signal with

power less than or equal to −96.32 dBFS is 4096 samples. For

each 6.02 dBFS increase in the signal power, the integration

period quadruples. The Min_period register can be programmed

from 1 to 31; 0 is not a valid value for this register.

Bit 2

This is the bypass bit that effectively shuts down the fine dc

correction block. When this bit is 1, no correction is performed.

Bit 1

This bit enables an interpolator that can smooth out the

updated estimate transition by a fixed interpolation by 256. This

is a linear interpolator that allows the correction block to gradually

shift between the old estimate and the new estimate to avoid

transients if there has been significant dc shift. If disabled, the

shift in correction values happens instantaneously, causing a

discontinuity in the signal; however, if the interpolator is enabled,

this shift occurs over 256 samples, preventing any large

discontinuities. The interpolator should not be enabled if

Min_period is set to less than 8 (a period of 256 samples). Use

of the interpolator is not recommended at this time, and this bit

should be set to 0.

Bit 0

When set to 1, this bit freezes the estimate of the dc correction

and resets the peak detector to the smallest possible signal state

(−138 dB peak signal). This way, the dc can be estimated once

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