AD9864 datasheet(21/48 Pages) AD

21 / 48 page

AD9864

Data Sheet

Rev. A | Page 20 of 47

The SSIORD register controls the output bit rate (fCLKOUT) of the

serial bit stream. fCLKOUT can be set equal to the modulator clock

frequency (fCLK) or an integer fraction of it. It is equal to fCLK divided

by the contents of the SSIORD register. Note that fCLKOUT must

be chosen such that it does not introduce harmful spurs within

the pass band of the target signal. Users must verify that the

output bit rate is sufficient to accommodate the required number

of bits per frame for a selected word size and decimation factor.

Idle (high) bits are used to fill out each frame.

24-BIT I AND Q, EAGC = 0, AAGC = X:48 DATA BITS

24-BIT I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS

16-BIT I AND Q, EAGC = 0, AAGC = X:32 DATA BITS

16-BIT I AND Q, EAGC = 0, AAGC = 0:32 DATA BITS

16-BIT I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS

RESET COUNT

I(15:0)

Q(15:0)

I(15:0)

ATTN(7:1)

Q(15:0)

I(15:0)

Q(15:0)

I(15:0)

Q(23:0)

I(23:0)

Q(23:0)

I(23:0)

ATTN(7:0)

SSI(5:1)

SSI(5:0)

Figure 32. SSI Frame Structure

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