Data Sheet

AD650

Rev. E | Page 7 of 20

CIRCUIT OPERATION

UNIPOLAR CONFIGURATION

The AD650 is a charge balance voltage-to-frequency converter.

In the connection diagram shown in Figure 4, or the block

diagram of Figure 5, the input signal is converted into an

exactly balanced by an internal feedback current delivered in

short, timed bursts from the switched 1 mA internal current

source. These bursts of current can be thought of as precisely

defined packets of charge. The required number of charge

packets, each producing one pulse of the output transistor,

depends upon the amplitude of the input signal. Because the

number of charge packets delivered per unit time is dependent

on the input signal amplitude, a linear voltage-to-frequency

transformation is accomplished. The frequency output is

furnished via an open collector transistor.

A more rigorous analysis demonstrates how the charge balance

voltage-to-frequency conversion takes place.

A block diagram of the device arranged as a V-to-F converter is

shown in Figure 5. The unit is comprised of an input integrator,

a current source and steering switch, a comparator, and a one

shot. When the output of the one shot is low, the current

amp; this is called the integration period. When the one shot

all the current to the summing junction of the op amp; this is

called the reset period. The two different states are shown in

Figure 6 and Figure 7 along with the various branch currents. It

should be noted that the output current from the op amp is the

same for either state, thus minimizing transients.

OP

AMP

COMP

IN

FREQ

OUT

OUT

ONE

SHOT

8

9

10

11

12

13

7

–15V

0.1µF

6

4

2

1

14

INPUT

OFFSET

TRIM

–0.6V

AD650

1mA

S1

5

+15V

R3

R1

3

DIGITAL

GROUND

ANALOG

GROUND

1µF

250kΩ

20kΩ

R2

0.1µF

Figure 4. Connection Diagram for V/F Conversion, Positive Input Voltage

S1

1mA ± 20%

AD650

+

–

INTEGRATOR

–0.6V

COMPARATOR

FREQUENCY

OUTPUT

ONE

SHOT

t

Figure 5. Block Diagram

S1

1mA

+

–

1mA

Figure 6. Reset Mode

S1

1mA

+

–

1mA

Figure 7. Integrate Mode

RESET

INTEGRATE

–0.6

∆V

t