Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) (Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(Note 1)

Input Current

Max

Other

01

mA

Input Voltage

PE CET Inputs

02

High Level Input Current

Other

20

m

A

PE CET Inputs

40

Low Level Input Current

54LS

b

04

mA

DM74

b

16

PE CET Inputs

b

08

mA

Short Circuit

54LS

b

20

b

100

mA

Output Current

(Note 2)

DM74

b

20

b

100

Supply Current with

31

mA

Outputs HIGH

Supply Current with

31

mA

Outputs LOW

L

Symbol

Parameter

Units

Min

Max

Maximum Clock Frequency

25

MHz

Propagation Delay

25

ns

CP to TC

21

Propagation Delay

24

ns

27

Propagation Delay

14

ns

CET to TC

23

Propagation Delay

28

ns

Functional Description

The ’LS160 and ’LS162 count modulo-10 in the BCD (8421)

sequence From state 9 (HLLH) they increment to state 0

(LLLL) The ’161 and ’163 count modulo-16 binary se-

quence From state 15 (HHHH) they increment to state 0

(LLLL) The clock inputs of all flip-flops are driven in parallel

through a clock buffer Thus all changes of the Q outputs

(except due to Master Reset of the ’LS160) occur as a re-

sult of and synchronous with the LOW-to-HIGH transition

of the CP input signal The circuits have four fundamental

modes of operation in order of precedence asynchronous

reset (’LS160) synchronous reset (’LS162) parallel load

count-up and hold Five control inputsMaster Reset (MR

’LS160) Synchronous Reset (SR ’LS162) Parallel Enable

(PE) Count Enable Parallel (CEP) and Count Enable Trickle

(CET)determine the mode of operation as shown in the

Mode Select Table A LOW signal on MR overrides all other

inputs and asynchronously forces all outputs LOW A LOW

signal on SR overrides counting and parallel loading and

allows all outputs to go LOW on the next rising edge of CP

A LOW signal on PE overrides counting and allows informa-

flip-flops on the next rising edge of CP With PE and MR

(’LS160) or SR (’LS162) HIGH CEP and CET permit count-

ing when both are HIGH Conversely a LOW signal on ei-

ther CEP or CET inhibits counting

The ’LS160A and ’LS162A use D-type edge-triggered flip-

flops and changing the SR PE CEP and CET inputs when

the CP is in either state does not cause errors provided that

the recommended setup and hold times with respect to the

rising edge of CP are observed

3