M24C16, M24C08, M24C04, M24C02, M24C01

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SUMMARY DESCRIPTION

grammable memory (EEPROM) devices are orga-

nized as 2048/1024/512/256/128 x 8 (M24C16,

M24C08, M24C04, M24C02, M24C01).

Figure 2. Logic Diagram

bi-directional data line and a clock line. The devic-

es carry a built-in 4-bit Device Type Identifier code

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start condition, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 2.),

terminated by an acknowledge bit.

When writing data to the memory, the device in-

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Table 1. Signal Names

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. At Power-up, the

the POR threshold value, and all operations are

disabled – the device will not respond to any com-

operating voltage, below the POR threshold value,

all operations are disabled and the device will not

respond to any command.

Table 7.) must be applied before applying any log-

ic signal.

Figure 3. DIP, SO, TSSOP and MLP Connections (Top View)

Note: 1. NC = Not Connected

2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.

AI02033

3

E0-E2

SDA

VCC

M24Cxx

WC

SCL

VSS

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

Supply Voltage

Ground

SDA

VSS

SCL

WC

VCC

/ E2

AI02034E

M24Cxx

1

2

3

4

8

7

6

5

/ E2

/ E2

/ E2

NC

/ E1

/ E1

/ E1

/ NC

NC

/ E0

/ E0

/ NC

/ NC

NC

/1Kb

/2Kb

/4Kb

/8Kb

16Kb