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M24C08-RDS3TG/W 数据表(PDF) 11 Page - STMicroelectronics

部件名 M24C08-RDS3TG/W
功能描述  16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM
PDF  29 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24C08-RDS3TG/W 数据表(HTML) 11 Page - STMicroelectronics

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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode Sequences
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9.) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
puts the contents of the addressed byte. The bus
master must not acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 9., without acknowledging the
byte.
DEV SEL *
BYTE ADDR
DEV SEL
DATA OUT 1
AI01942
DATA OUT N
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
DATA OUT N
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
DEV SEL *
DATA OUT 1
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK



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