3

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

Pinout Table

Pin Name

Characteristics

Desctription

AGND

Ground

Analog ground

1.8V nominal

Analog power

CK

Differential Input

Clock input with a (10K - 100KΩ) pulldown resistor

CK

Differential Input

Complementary clock input with a (10K - 100KΩ) pulldown resistor

Differential Input

Complementary feedback clock input

Differential Input

Feedback clock input

Differenital Output

Complementary Feedback clock output

Differential Output

Feedback clock output

OE

LVCMOS input

Output enable (async.)

OS

LVCMOS input

GND

Ground

Ground

1.8V nominal

Logic and output power

Y[0:9]

Differential Outputs

Clock outputs

Y[0:9]

Differential Outputs

Complementary clock outputs

NB

No Ball (VFBGA only)

Function Table

Inputs

Outputs

PLL State

OE

OS

CK

CK

Y

Y

FBOUT

FBOUT

GND

H

X

L

H

L

H

L

H

Bypass/Off

GND

H

X

H

L

H

L

H

L

Bypass/Off

GND

L

H

L

H

L

H

Bypass/Off

GND

L

L

H

L

Y7 active

Y7 active

H

L

Bypass/Off

1.8V (nom)

L

H

L

H

L

H

On

1.8V (nom)

L

L

H

L

Y7 active

Y7 active

H

L

On

1.8V (nom)

H

X

L

H

L

H

L

H

On

1.8V (nom)

H

X

H

L

H

L

H

L

On

1.8V (nom)

X

X

L

L

Off

1.8V (nom)

X

X

H

H

Reserved

Notes:

1.