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MP7610AS 数据表(PDF) 5 Page - Exar Corporation |
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MP7610AS 数据表(HTML) 5 Page - Exar Corporation |
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5 / 16 page  MP7610 5 Rev. 4.01 25 °C Tmin to Tmax ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Settling from LD tsd 30 50 50 ms ZS to FS (20 V Step) to VDAC Out1 5k, 50pF load Channel-to-Channel Crosstalk6 CT 0.04 LSB DC Digital Feedthrough1, 6 Q --70 dB CLK and Data to VOUTi Power Supply Rejection Ratio PSRR 5 ppm/% DVEE & DVCC = ±5%, ppm of FS REFERENCE INPUTS Impedance of VREF REF 350 700 1.05k 350 1.05k W See Application Hints for Driving the reference input VREF Voltage1, 2 VREF 3.5 6 V DIGITAL INPUTS3 Logic High VIH 2.4 V Logic Low VIL 0.8 V Input Current IL ±10 mA Input Capacitance1 CL 8 pF ANALOG OUTPUTS Output Swing --VEE +1.4 VCC --1.4 V Output Drive Current --5 5 mA Output Impedance RO 1 W Output Short Circuit Current ISC 25 mA +FS to AGND 30 mA +FS to VEE 40 mA --FS to AGND 55 mA --FS to VCC DIGITAL OUTPUTS Output High Voltage VOH 4.5 V Output Low Voltage VOL 0.5 V POWER SUPPLIES VCC Voltage5 VCC VREF+1.5 12 12.75 VREF+1.5 12.75 V VEE Voltage5 VEE --12.75 --12 --5 --12.75 --5 V DVDD Voltage DVDD 4.5 5 5.5 4.5 5.5 V Positive Supply Current ICC 8 10 10 mA Bipolar zero Negative Supply Current IEE 15 20 20 mA Bipolar zero Digital Supply Current IDD 2 2 mA Bipolar zero Power Dissipation PDISS 320 420 450 mW Bipolar zero ANALOG GROUND CURRENT Per Channel1 IAGND ±60 mA See Application Notes DIGITAL TIMING SPECIFICATIONS1,4 VIL = 0, VIH = 5.0, CL = 20 pF Input Clock Pulse Width tCH, tCL 60 ns Data Setup Time tDS 15 ns Data Hold Time tDH 15 ns CLK to SDO Propagation Delay tPD 40 ns DAC Register Load Pulse Width tLD 45 ns Preset Pulse Width tPR 65 ns Clock Edge to Load Time tCKLD1 140 ns Note: tLD and tCKLD2 cannot both tCKLD2 0 be min. since tCKLD1=tCKLD2+tLD LD Falling Edge to SDO tHZ1 50 ns Tri-state Enable |
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