MP7610

8

Rev. 4.01

The MP7610 is equipped with a serial data (3-wire standard)

and board wire (space). If the LD signal is high, the CLK signal

loads the digital input bits (SDI) into the shift register (4 bits ad-

dress A3 to A0 plus 14 bits data D13 to D0 for the MP7610). The

LD signal going low loads the data into the selected DAC. The

LD signal going low also disables the serial data (SDI), output

(SDO tri-stated) and the CLK input. This design tremendously

reduces digital noise and glitch transients into the DACs due to

free running CLK and SDI. Note also that the preset signal

(RST) resets all analog outputs to 0 volt regardless of digital in-

puts.

A3 A2 A1 A0

X

X

X

X

1

1

DAC 0

0

0

0

1

DAC 1

0

0

1

0

DAC 2

0

0

1

1

DAC 3

0

1

0

0

DAC 4

0

1

0

1

DAC 5

0

1

1

0

DAC 6

0

1

1

1

DAC 7

1

0

0

0

X

X

X

X

X

X

X

X

1

1

1

1

1

1

1

1

X

X

X

X

X

X

0

1

1

1

0

1

1

1

1

1

1

Function

LD

CLK

RST

Shift Data In

and Out

Repeat

Load DACs

Reset all DACs

to 0 V

No Operation

No Operation

Table 1. Digital Function Truth Table

Serial In/Serial Out

X

X

X

X

X

SDI

Data Input

Valid

X

X

X

X

X

X

X

X

X

X

X

SDO

Data Output

Valid

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

0

0

0

0

No Operation

Stop Shifting

Data In and

Out

X

X

X

X

0

1

Hi-Z

X

X

X

No Operation

Note: For timing information See Electrical Characteristics.

Table 2. MP7610 Ideal DAC Output vs. Input Code

Hex Code

O O O O

1 F F F

) = --1.22 mV

Binary Code

16384

)

(Vr = +5 V)

00000000000000

01111111111111

16382

16384

10000000000000

16384

16384

2 O O O

) = 0

10000000000001

16386

16384

2 O O 1

) = 1.22 mV

11111111111111

32766

16384

3 F F F

) = 9.99878

Note: See Electrical Characteristics for real system accuracy