M95640-RBN6P datasheet(15/39 Pages) STMICROELECTRONICS

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M95640, M95320

Figure 12. Write Status Register (WRSR) Sequence

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction al-

lows new values to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded and executed, the device sets

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the data byte on Serial

Data Input (D).

The instruction sequence is shown in Figure 12.

The Write Status Register (WRSR) instruction has

no effect on b6, b5, b4, b1 and b0 of the Status

Chip Select (S) must be driven High after the rising

edge of Serial Clock (C) that latches in the eighth

bit of the data byte, and before the next rising edge

of Serial Clock (C). Otherwise, the Write Status

soon as Chip Select (S) is driven High, the self-

timed Write Status Register cycle (whose duration

is tW) is initiated. While the Write Status Register

cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 dur-

ing the self-timed Write Status Register cycle, and

is 0 when it is completed. When the cycle is com-

pleted, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP1, BP0) bits, to define the size of the

area that is to be treated as read-only, as defined

in Table 2.

The Write Status Register (WRSR) instruction also

allows the user to set or reset the Status Register

Write Disable (SRWD) bit in accordance with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected Mode (HPM). The Write Status Register

(WRSR) instruction is not executed once the Hard-

ware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable

(SRWD) and Block Protect (BP1, BP0) bits are fro-

zen at their current values from just before the

start of the execution of Write Status Register

(WRSR) instruction. The new, updated, values

take effect at the moment of completion of the ex-

ecution of Write Status Register (WRSR) instruc-

tion.

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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