REV. B

AD8380

–12–

SXGA and Beyond

Very high resolution display systems can be built using the E/

O

XGA system as a model. By using four AD8380s, twenty-four

columns can be driven together for an SXGA display. Two would

be designated for even columns and two for odd. Four separate

STSQ signals would be used to coordinate data loading with a

single XFR to synchronize updating of output voltages.

Using a single external voltage source to drive the VREF inputs

on all drivers for a particular color and a single voltage source

for all their VMID inputs, will guarantee matching for all channels.

The exceptional accuracy of the AD8380’s transfer function will

ensure that high channel count systems can be built without fear of

image artifacts resulting from channel-to-channel matching errors.

Direct Channel Loading

For debug or characterization purposes, it may be desirable to

load data directly into a single channel without requiring exercise

of the STSQ and XFR inputs. This can be done by applying

dc logic high levels to the STSQ and XFR inputs, and addressing

the desired channel through the A[0:2] inputs. Data will then

be loaded into the selected channel on each falling edge of the

CLK signal.

The maximum rate at which a channel can be updated will be

limited by the settling time of the output amplifiers.

Addressed Channel Loading

The direct channel loading method can be extended. Channels

may be loaded in an arbitrary sequence through the use of an

active XFR signal with STSQ set to a high level. Use the A[0:2]

inputs to define the desired channel sequence. Data will be loaded

on the falling edge of CLK into the channel whose address was

valid on the preceding rising edge of CLK. All channel outputs

are then updated together by qualification of a valid XFR signal.

See Figure 9 for timing details.

t

1

t

2

50

1

5

t

5

DB[0:9]

CLK

XFR

t

6

t

8

t

9

0

IN THIS CASE, INPUT LATCHES ARE LOADED IN THE ORDER SELECTED

BY A[0:2], THEN DACs ARE UPDATED TOGETHER BY XFR.

A[0:2]

Figure 9. Addressed Channel Timing (E/

O = HIGH,

STSQ/CS = HIGH)

Standby Mode

A high level applied to the standby (STBY) input will turn off

most of the internal circuitry, dropping the quiescent power

dissipation to a few milliwatts. Since both digital and analog

circuits are debiased, all stored data will be lost. Upon returning

STBY to a low level, normal operation is restored.

APPLICATION

The AD8380 is a mixed-signal, high speed, very accurate device

with multiple channels. In order to realize its specifications, it is

essential to use a properly designed circuit board.

Layout and Grounding

The analog and digital sections of the AD8380 are pinned

out on approximately opposite sides of the package. When

laying out a circuit board, please keep these sections separate

from each other to minimize crosstalk and noise coupling of

the digital input signals into the analog outputs.

All signal trace lengths should be made as short and direct as

possible to prevent signal degradation due to parasitic effects.

Please note that digital signals should not cross or be routed

near analog signals.

It is imperative to provide a solid ground plane under and

around the part. All of the ground pins of the part should be

directly connected to the ground plane with no extra signal

path length. For conventional operation, this includes the

pins DVEE, AVEEDAC, AVEEBIAS, AVEE0, AVEE1,2;

AVEE3,4; and AVEE5. The return currents for any of the sig-

nals for the part should be routed close to the ground pin for

that section to prevent stray signals from appearing on other

ground pins.

Power Supply Bypassing

The AD8380 has several power supply and reference voltages

that must be properly bypassed to the ground plane for opti-

mum performance. The bypass capacitor for each supply pin, as

well as VREFHI, VREFLO, and VMID, should be connected as

close as possible to the IC pins and directly to the ground plane.

A 0.1

µF capacitor, preferably a ceramic chip, should be used to

minimize lead length.

To provide low frequency, high current bypassing, larger value

tantalum capacitors should also be used. These should be con-

nected from the supply to ground, but it is not necessary to place

these close to the IC pins. Stray inductance will not greatly affect

their performance. The high current outputs should be bypassed

with these capacitors. It is recommended that two 22

µF tantalum

capacitors be placed from the AVCC supply to ground at either

end of the output side of the IC. AVCCBIAS and AVCCDAC

should each have a 10

µF tantalum bypass capacitor to ground.

See Figure 10.

VREFHI Reference Distribution

In a system that uses more than one AD8380 per color, it is

important that all of the AD8380 devices operate from equal

reference voltages to ensure that the video outputs are well

matched. VREFLO is not a concern due to its high input resis-

tance and very low bias current. Therefore, it is not likely that

there will be significant dc voltage drops in the circuit traces to that

supply. It is recommended to have good local supply bypassing

at each AD8380 from their respective VREFLOs to ground.

The higher input current that flows in the VREFHI circuit

requires that this be laid out more carefully. VREFHI connects

internally to a 20 k

Ω resistor for each of the six channels to provide

an input resistance of about 3.3 k

Ω. Thus with a (VREFHI –

VREFLO) voltage of 2.5 V (to yield a VFS of 5.0 V ), about

750

µA will flow into each VREFHI circuit.