AP2002

Synchronous PWM Controller

Anachip Corp.

www.anachip.com.tw

Rev. 0.2 Apr 14, 2004

5/7

Function Description

Synchronous Buck Converter

voltage-mode

pulse

width

modulated

(PWM)

controller. This section has all the features required

to build a high efficiency synchronous buck

converter, including “Power Good” flag, shutdown,

and cycle-by-cycle current limit.

The output voltage of the synchronous converter is

set and controlled by the output of the error

amplifier. The external resistive divider reference

voltage is derived from an internal trimmed

band-gap voltage reference. The inverting input of

the error amplifier receives its voltage from the

SENSE pin.

The internal oscillator uses an on-chip capacitor

and trimmed precision current sources to set the

oscillation frequency to 200KHz. The triangular

output of the oscillator sets the reference voltage at

the inverting input of the comparator. When the

oscillator output voltage drops below the error

amplifier output voltage, the comparator output

goes high. This pulls DRVL low, turning off the

low-side FET, and DRVH is pulled high, turning on

the high-side FET (once the cross-current control

allows it). When the oscillator voltage rises back

above the error amplifier output voltage, the

comparator output goes low. This pulls DRVH low,

turning off the high-side FET, and DRVL is pulled

high, turning on the low-side FET (once the

cross-current control allows it).

As SENSE increases, the output voltage of the

error amplifier decreases. This causes a reduction

in the on-time of the high-side MOSFET connected

to DRVH, hence lowering the output voltage.

Under Voltage Lockout

The under voltage lockout circuit of the AP2002

assures that the high-side MOSFET driver outputs

remain in the off state whenever the supply voltage

falls below 4.1V. Normal operation resumes once

Over-Voltage Protection

The over-voltage protection pin (OVP) is high only

when the voltage at SENSE is 20% higher than the

target value programmed by the external resistor

divider. The OVP pin is internally connected to a

PNP’s collector.

Power Good

The power good function is to confirm that the

regulator outputs are within +/- 10% of the

programmed level. PWRGD remains high as long

as this condition is met. PWRGD is connected to an

internal open collector NPN transistor.

Soft Start

Initially, SS/ SHDN sources 10uA of current to

charge an external capacitor. The outputs of the

error

amplifiers

are

clamped

to

a

voltage

proportional to the voltage on SS/ SHDN . This limits

the on-time of the high-side MOSFET, thus leading

to a controlled ramp-up of the output voltages.

The current limit threshold is setting by connecting

The voltage drop across this resistor is due to the

200uA internal sink sets the voltage at the pin.

This voltage is compared to the voltage at the

PHASE node. This comparison is made only when

the high-side drive is high to avoid false current limit

triggering due to un-contributing measurements

from the MOSFETs off-voltage. When the voltage at

PHASE is less than the voltage at OCSET, an

over-current condition occurs and the soft start

cycle is initiated. The synchronous switch turns off

and SS/ SHDN

starts to sink 2uA. When

SS/ SHDN reaches 0.8V, it then starts to source

10uA and a new cycle begins.