AX88615P datasheet(2/26 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88615P 5-Port 10/100Mb Switch Controller

PRELIMINARY

CONTENTS

1.0 AX88615 OVERVIEW ....................................................................................................................................... 4

1.1 GENERAL DESCRIPTION...................................................................................................................................... 4

1.2 AX88615 BLOCK DIAGRAM: .............................................................................................................................. 4

1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 5

2.0 PIN DESCRIPTION ........................................................................................................................................... 6

2.1 MII/RMII INTERFACE FOR SWITCH PORTS............................................................................................................ 6

2.1.1 Switch Port 0.............................................................................................................................................. 6

2.1.2 Switch Port 1.............................................................................................................................................. 7

2.1.3 Switch Port 2.............................................................................................................................................. 7

2.1.4 Switch Port 3.............................................................................................................................................. 8

2.1.5 Switch Port 4.............................................................................................................................................. 8

2.2 LED DISPLAY.................................................................................................................................................... 9

2.3 BUFFER MEMORY PINS GROUP ............................................................................................................................. 9

2.4 MISCELLANEOUS.............................................................................................................................................. 10

2.5 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 11

3.0 FUNCTIONAL DESCRIPTION ..................................................................................................................... 13

3.1 BASIC OPERATION............................................................................................................................................ 13

3.2 PACKET FILTERING AND FORWARDING PROCESS................................................................................................ 13

3.3 MAC ADDRESS LEARNING AND AGING PROCESS .............................................................................................. 13

3.4 FLOW CONTROL PROCESS ................................................................................................................................ 13

4.0 INTERNAL REGISTERS ................................................................................................................................ 15

5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 16

5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 16

5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 16

5.3 DC CHARACTERISTICS ..................................................................................................................................... 16

5.4 AC SPECIFICATIONS ......................................................................................................................................... 17

5.4.1 LCLK ....................................................................................................................................................... 17

5.4.2 Reset Timing ............................................................................................................................................ 17

5.4.3 RMII Interface Timing Tx & Rx................................................................................................................ 18

5.4.4 MII Interface Timing Tx & Rx .................................................................................................................. 19

5.4.5 SSRAM Read Cycle Timing ...................................................................................................................... 20

5.4.6 SSRAM Write CycleTiming....................................................................................................................... 21

5.4.7 LED DISPLAY ......................................................................................................................................... 22

5.4.8 LED Display After Reset .......................................................................................................................... 22

6.0 PACKAGE INFORMATION........................................................................................................................... 23

APPENDIX A: SYSTEM APPLICATIONS.......................................................................................................... 24

A.1 AX88615 AS 5-PORT STANDALONE SOHO SWITCH........................................................................................... 24

A.2 AX88615 FOR IP ROUTER APPLICATION ........................................................................................................... 24

A.3 AX88615 AS BACKEND OF DUAL SPEED REPEATERS........................................................................................... 25

APPENDIX B: DESIGN NOTE ............................................................................................................................. 26

B.1 USING STATION MANAGEMENT (STA) CONNECTION ........................................................................................ 26

B.2 USING MII I/F CONNECTS TO MAC.................................................................................................................. 26

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