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GND

1Y0

1Y1

1Y2

GND

GND

1Y3

1Y4

1G

2Y4

CLK

2Y0

2Y1

GND

GND

2Y2

2Y3

2G

PW PACKAGE

(TOP VIEW)

DESCRIPTION

CDCVF310

SCAS771A – AUGUST 2004 – REVISED AUGUST 2004

2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER

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High-Performance 1:10 Clock Driver for

General-Purpose Applications

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•

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Input Clock Up To 200 MHz (See Figure 7)

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Operating Temperature Range –40

°C to 85°C

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Output Enable Glitch Suppression

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Distributes One Clock Input to Two Banks of

Five Outputs

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Packaged in 24-Pin TSSOP

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Pin-to-Pin Compatible to the CDCVF2310,

Except the R = 22-

Ω Series Damping

Resistors at Yn

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five

outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless

of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a

low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on

the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins

(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a

2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable

sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from –40

°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.