DS3141 datasheet(49/88 Pages) DALLAS

49 / 88 page

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

49 of 88

BSRL

BERT Status Register Latched

39h

Bit #

Name

N/A

RA1L

RA0L

BEDL

BBCOL

BECOL

SYNCL

Default

—

Note: See Figure 7-6 for details on the interrupt logic for the status bits in the BSRL register.

Bit 0: Synchronization Status Latched (SYNCL). This latched status bit is set to 1 when the SYNC status bit in

the BSR register changes state (low to high or high to low). To determine if this bit was set because of finding

synchronization or losing synchronization, read the SYNC real-time status bit in the BSR register. SYNCL is

cleared when the host processor writes a 1 to it and is not set again until SYNC changes state again. When

SYNCL is set, it can cause a hardware interrupt to occur if the SYNCIE bit in the BSRIE register and the BERTIE

bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the

interrupt-enable bits are cleared.

Bit 1: BERT Error-Counter Overflow Latched (BECOL). This latched status bit is set to 1 when the BECO status

bit in the BSR register goes high. BECOL is cleared when the host processor writes a one to it and is not set again

until BECO goes high again. When BECOL is set, it can cause a hardware interrupt to occur if the BECOIE bit in

the BSRIE register and the BERTIE bit in the MSRIE register are both set to a 1. The interrupt is cleared when this

bit is cleared or one or both of the interrupt-enable bits are cleared.

Bit 2: BERT Bit-Counter Overflow Latched (BBCOL). This latched status bit is set to 1 when the BBCO status bit

in the BSR register goes high. BBCOL is cleared when the host processor writes a 1 to it and is not set again until

BBCO goes high again. When BBCOL is set, it can cause a hardware interrupt to occur if the BBCOIE bit in the

BSRIE register and the BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is

cleared or one or both of the interrupt-enable bits are cleared.

Bit 3: Bit Error-Detected Latched (BEDL). This latched status bit is set to 1 when a bit error is detected. The

receive BERT must be in synchronization to detect bit errors. BEDL is cleared when the host processor writes a 1

to it. When BEDL is set it can cause a hardware interrupt to occur if the BEDIE bit in the BSRIE register and the

BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both

of the interrupt-enable bits are cleared.

Bit 4: Receive All-Zeros Latched (RA0L). This latched status bit is set to 1 when the RA0 bit in the BSR register

is set. RA0L is cleared when the host processor writes a 1 to it. RA0L cannot cause an interrupt.

Bit 5: Receive All-Ones Latched (RA1L). This latched status bit is set to 1 when the RA1 bit in the BSR register is

set. RA1L is cleared when the host processor writes a 1 to it. RA1L cannot cause an interrupt.

DS3141 数据表(PDF) 49 Page - Dallas Semiconductor

DS3141 数据表(HTML) 49 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载