AD7453

Rev. B | Page 16 of 20

POWER-UP TIME

The power-up time of the AD7453 is typically 1 µs, which

means that with any frequency of SCLK up to 10 MHz, one

dummy cycle is always sufficient to allow the device to power

up. Once the dummy cycle is complete, the ADC is fully

powered up and the input signal is acquired properly. The quiet

bus goes back into three-state after the dummy conversion to

the next falling edge of CS.

When running at the maximum throughput rate of 555 kSPS,

the AD7453 powers up and acquires a signal within ±0.5 LSB in

one dummy cycle. When powering up from power-down mode

with a dummy cycle, as in Figure 26, the track and-hold, which

was in hold mode while the part was powered down, returns to

track mode after the first SCLK edge the part receives after the

falling edge of CS. This is shown as Point A in Figure 26.

Although at any SCLK frequency one dummy cycle is sufficient

mean that a full dummy cycle of 16 SCLKs must always elapse

power up the device and acquire the input signal.

For example, if a 5 MHz SCLK frequency is applied to the ADC,

the cycle time is 3.2 µs (i.e., 1/(5 MHz) × 16). In one dummy

However after 1 µs with a 5 MHz SCLK, only five SCLK cycles

have elapsed. At this stage, the ADC is fully powered up and the

signal acquired. So in this case, CS can be brought high after the

to initiate the conversion.

When power supplies are first applied to the AD7453, the ADC

may either power up in the power-down mode or normal mode.

Because of this, it is best to allow a dummy cycle to elapse to

ensure that the part is fully powered up before attempting a

valid conversion. Likewise, if the user wants the part to power

up in power-down mode, the dummy cycle may be used to

ensure the device is in power-down mode by executing a cycle

such as that shown in Figure 25. Once supplies are applied to

the AD7453, the power-up time is the same as that when

powering up from power-down mode. It takes approximately

1 µs to power up fully if the part powers up in normal mode. It

is not necessary to wait 1 µs before executing a dummy cycle to

ensure the desired mode of operation. Instead, the dummy cycle

can occur directly after power is supplied to the ADC. If the

first valid conversion is then performed directly after the

dummy conversion, care must be taken to ensure that adequate

acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part returns to track mode upon the first SCLK edge

applied after the falling edge of CS. However, when the ADC

powers up initially after supplies are applied, the track-and-hold

is already in track mode. This means (assuming one has the

facility to monitor the ADC supply current) that if the ADC

powers up in the desired mode of operation and thus a dummy

cycle is not required to change the mode, then a dummy cycle is

not required to place the track-and-hold into track.

CS

SCLK

SDATA

1

10

16

1

10

16

A

THIS PART IS FULLY POWERED

PART BEGINS

TO POWER UP

INVALID DATA

VALID DATA

Figure 26. Exiting Power-Down Mode