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M41ST87W 数据表(PDF) 20 Page - STMicroelectronics |
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M41ST87W 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 42 page ![]() M41ST87Y, M41ST87W 20/42 Figure 19. Tamper Output Timing (with CLR1EXT or CLR2EXT = '1') Note: 1. If connected to a negative charge pump device, this pin must be isolated from the charge pump by using both n-channel and p- channel MOSFETs as illustrated in Figure 20., page 21. 2. If the device is in battery back-up; NOT on VCC (see RAM Clear External (CLR1EXT and CLR2EXT), page 18). 3. If TIEX = '1.' 4. If ABE = '1.' Table 5. Tamper Detect Timing Note: 1. With input capacitance = 70pF and resistance = 50 Ω. 2. If the OF Bit is set, tCLRD(min) = 0.5ms. Symbol Parameter CLRPW1 CLRPW0 Min Typ Max Unit tCLRD (1) Tamper RAM Clear Ext Delay X X 1.0(2) 1.5 2.0 ms tCLR Tamper Clear Timing 00 1 s 01 4 s 10 8 s 11 16 s TPCLR VOUT (1) RST Tamper Event (TB Bit set) High-Z(2) trec tCLR tCLRD AI07083 ECON IRQ/OUT (3) High-Z (4) |
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