M41ST87YMX6TR datasheet(18/42 Pages) STMICROELECTRONICS

18 / 42 page

M41ST87Y, M41ST87W

18/42

Tamper Detect Sampling (TDS1 and TDS2).

This bit selects between a 1Hz sampling rate or

constant monitoring of the Tamper Input Pin(s) to

detect a tamper event when the Normally Closed

switch mode is selected. This allows the user to re-

duce the current drain when the TEBX Bit is en-

abled while the device is in battery backup (see

Table 4., page 18 and Figure 17., page 19). Sam-

pling is disabled if the TCMX Bit is set to logic '1'

(Normally Open). In this case the state of the

TDSX Bit is a “Don’t care.”

Note: The crystal oscillator must be “On” for sam-

pling to be enabled.

Tamper Current Hi/Tamper Current Lo (TCHI/

TCLO1 and TCHI/TCLO2). This bit selects the

strength of the internal pull-up or pull-down used

during the sampling of the Normally Closed condi-

tion. The state of the TCHI/TCLOX Bit is a “Don’t

care” for Normally Open (TCMX = '1') mode (see

Figure 18., page 19).

RAM Clear (CLR1 and CLR2). When either of

these bits and the TEBX Bit are set to a logic '1,'

the internal 128 bytes of user RAM (see Figure

15., page 17) will be cleared to all zeros in the

event of a tamper condition. The 128 bytes of user

RAM will be deselected (invalid data will be read)

until the corresponding TEBX Bit is reset to '0.'

RAM Clear External (CLR1EXT and CLR2EXT).

When either of these bits are set to a logic '1' and

the TEBX Bit is also set to logic '1,' the external

SRAM will be cleared and the RST output enabled

(see

Figure

15., page 17

and

Figure

20., page 21).

Note: The reset output resulting from a tamper

event will be the same as a reset resulting from a

power-down condition, a watchdog time-out, or a

manual reset (RSTIN1 or RSTIN2).

This is accomplished by forcing TPCLR high, which

if used to control the inhibit pin of the DC regulator

(see Figure 20., page 21) will also switch off VOUT,

depriving the external SRAM of power to the VCC

pin. VOUT will automatically be disconnected from

the battery if the tamper occurs during battery

back-up (see Figure 19., page 20). By inhibiting

the DC regulator, the user will also prevent other

inputs from sourcing current to the external SRAM,

allowing it to retain data.

The user may optionally connect an inverting

charge pump to the VCC pin of the external SRAM

(see Figure 20., page 21). Depending on the pro-

cess technology used for the manufacturing of the

external SRAM, clearing the memory may require

varying durations of negative potential on the VCC

pin. This device configuration will allow the user to

program the time needed for their particular appli-

cation. Control Bits CLRPW0 and CLRPW1 deter-

mine the duration TPCLR will be enabled (see

Figure 19., page 20 and Table 5., page 20).

Note: When using the inverting charge pump, the

user must also provide isolation in the form of two

additional small-signal power MOSFETs. These

will isolate the VOUT pin from both the negative

voltage generated by the charge pump during a

tamper condition, and from being pulled to ground

by the output of the charge pump when it is in shut-

down mode (SHDN = logic low). The gates of both

MOSFETs should be connected to TPCLR as

shown in Figure 20., page 21. One n-channel en-

hancement MOSFET should be placed between

the output of the inverting charge pump and the

VOUT of the M41ST87. The other MOSFET should

be an enhancement mode p-channel, and placed

between VOUT of the M41ST87 and VCC of the ex-

ternal SRAM. When TPCLR goes high after a

tamper condition occurs, the n-channel MOSFET

will turn on and the p-channel will turn off. During

normal operating conditions, TPCLR will be low

and the p-channel will be on, while the n-channel

will be off.

Table 4. Tamper Detection Current (Normally Closed - TCMX = '0')

Note: 1. When calculating battery lifetime, this current should be added to IBAT current listed in Table 17., page 37.

2. Per Tamper Detect Input

TDSX

TCHI/TCLOX

Tamper Circuit Mode

Current at 3.0V (typ)(1,2)

Unit

Continuous Monitoring / 10M

Ω pull-up/-down

0.3

µA

Continuous Monitoring / 1M

Ω pull-up/-down

3.0

µA

Sampling (1Hz) / 10M

Ω pull-up/-down

0.3

Sampling (1Hz) / 1M

Ω pull-up/-down

3.0

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