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M5450, M5451

Table 1. Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

FUNCTIONAL DESCRIPTION

Both the M5450 and the M5451 are specially de-

signed to operate 4 or 5-digit alphanumeric dis-

plays with minimal interface with the display and

the data source. Serial data transfer from the data

source to the display driver is accomplished with 2

signals, serial data and clock. Using a format of a

leading "1" followed by the 35 data bits allows data

transfer without an additional load signal. The 35

data bits are latched after the 36th bit is complete,

thus providing non-multiplexed, direct drive to the

display.

Outputs change only if the serial data bits differ

from the previous time.

Display brightness is determined by control of the

output current LED displays.

A 1nF capacitor should be connected to bright-

ness control, pin 19, to prevent possible oscilla-

tions.

A block diagram is shown in Figure 3. For the

M5450 a DATA ENABLE is used instead of the

35th output. The DATA ENABLE input is a metal

option for the M5450.

The output current is typically 20 times greater

than the current into pin 19, which is set by an ex-

ternal variable resistor. There is an internal limiting

resistor of 400W nominal value.

Figure 4 shows the input data format. A start bit of

logical "1" precedes the 35 bits of data. At the 36th

clock a LOAD signal is generated synchronously

with the high state of the clock, which loads the 35

bits of the shift registers into the latches.

At the low state of the clock a RESET signal is

generated which clears all the shift registers for

the next set of data. The shift registers are static

master-slave configurations. There is no clear for

the master portion of the first shift register, thus al-

lowing continuous operation.

There must be a complete set of 36 clocks or the

shift registers will not clear.

When power is first applied to the chip an internal

power ON reset signal is generated which resets

all registers and all latches. The START bit and the

first clock return the chip to its normal operation.

Bit 1 is the first bit following the start bit and it will

appear on Pin 18. A logical "1" at the input will turn

on the appropriate LED.

Figure 5 shows the timing relationship between

Data, Clock and DATA ENABLE.

A max clock frequency of 0.5MHz is assumed. For

applications where a lesser number of outputs are

used, it is possible to either increase the current

per output or operate the part at higher than 1V

The following equation can be used for calcula-

tions.

where :

124°C/W = thermal coefficient of the package

The above equation was used to plot Figure 6, Fig-

ure 7 and Figure 8.

Symbol

Parameter

Value

Unit

Supply Voltage

– 0.3 to 15

V

Input Voltage

– 0.3 to 15

V

Off State Output Voltage

15

V

Output Sink Current

40

mA

Total Package Power Dissipation at 25°C

1

W

Total Package Power Dissipation at 85°C

560

mW

Junction Temperature

150

°C

Operating Temperature Range

– 25 to 85

°C

Storage Temperature Range

– 65 to 150

°C