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AD7663AST 数据表(PDF) 5 Page - Analog Devices |
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AD7663AST 数据表(HTML) 5 Page - Analog Devices |
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5 / 25 page  REV. B AD7663 –4– TIMING SPECIFICATIONS (continued) Parameter Symbol Min Typ Max Unit Refer to Figures 17 and 18 (Master Serial Interface Modes) 1 CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert t28 See Table II µs CNVST LOW to SYNC Asserted Delay t29 1.25 µs (Master Serial Read after Convert) SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figures 19 and 21 (Slave Serial Interface Modes) External SCLK Setup Time t31 5ns External SCLK Active Edge to SDOUT Delay t32 316 ns SDIN Setup Time t33 5ns SDIN Hold Time t34 5ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 2In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode. Specifications subject to change without notice. IOH 500 A 1.6mA IOL TO OUTPUT PIN 1.4V CL 60pF* *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. Figure 1. Load Circuit for Digital Interface Timing t DELAY t DELAY 0.8V 0.8V 0.8V 2V 2V 2V Figure 2. Voltage Reference Levels for Timing Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0011 DIVSCLK[0] 0101 Unit SYNC to SCLK First Edge Delay Minimum t18 420 2020 ns Internal SCLK Period Minimum t19 25 50 100 200 ns Internal SCLK Period Maximum t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 15 25 50 100 ns Internal SCLK LOW Minimum t21 9.5 24 49 99 ns SDOUT Valid Setup Time Minimum t22 4.5 22 22 22 ns SDOUT Valid Hold Time Minimum t23 2430 90 ns SCLK Last Edge to SYNC Delay Minimum t24 360 140 300 ns BUSY HIGH Width Maximum t28 2 2.5 3.5 5.75 µs |
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