REV. A

AD7709

–15–

Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H)

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-

tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the

Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the

data stream. The number in brackets indicates the power-on-reset default status of that bit.

Table VI. Status Register Bit Designations

Bit

Bit

Location

Name

Description

SR7

RDY

Ready Bit for ADC.

Set when data is written to the ADC data register.

The RDY bit is cleared automatically after the ADC data register has been read or a period of time before

the data register is updated with a new conversion result.

SR6

0This bit is automatically cleared.

SR5

0This bit is automatically cleared.

SR4

0This bit is automatically cleared.

SR3

ERR

ADC Error Bit. This bit is set at the same time as the RDY bit.

Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.

Error sources include Overrange, Underrange.

Cleared by a write to the mode bits to initiate a conversion.

SR2

0This bit is automatically cleared.

SR1

STBY

Standby Bit Indication.

When this bit is set, the AD7709 is in power-down mode.

This bit is cleared when the ADC is powered up.

SR0

LOCK

PLL Lock Status Bit.

Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact

sampling frequencies, etc., the LOCK bit should be interrogated and the result discarded if the LOCK

bit is 0.

7

R

S6

R

S5

R

S4

R

S3

R

S2

R

S1

R

S0

R

S

)

0

(

Y

D

R)

0

(

0)

0

(

0)

0

(

0)

0

(

R

R

E)

0

(

0)

0

(

Y

B

T

S)

0

(

K

C

O

L