ACE25AC100G

SPI NOR FLASH

VER 1.1

3

Block Diagram

Uniform Block Sector Architecture

ACE25AC100G 64K Bytes Block Sector Architecture

Block

Sector

Address Range

1

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

0

15

00F000H

00FFFFH

……

……

……

0

000000H

000FFFH

Device Operation

The ACE25AC100G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip

Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are

supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of

SCLK.